Dual supply ECL to TTL translator

Details Dual supply ECL to TTL translator Dual supply ECL to TTL translator

1989-07-03

1991-03-05

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307455, 307456, 307542, 307546, H03K 19086, H03B 104

Patent

active

049980297

ABSTRACT:
An ECL to TTL translator converts a signal from ECL logic levels to TTL compatible logic levels without introducing current spikes in the output signal during logic translations. The ECL input signal is transformed into first and second differentially related currents which develop first and second voltages for biasing first and second switching circuits which in turn generate first and second complementary control signals. The sum total of the differentially related currents are limited to a predetermined magnitude blocking simultaneously assertion of the control signals. An output stage includes an upper and lower transistors each responsive to the first and second control signal respectively for developing a TTL high and TTL low output signal. The first and second switching circuits inhibit simultaneous conduction of the upper and lower transistors of the output stage preventing undesirable current spikes in the output signal thereof.

REFERENCES:
IBM Tech. Dis. Bul., "ECL to TTL Translator Driven", Froment et al., vol. 21, No. 10, 3/79.
IBM Tech. Disc. Bul., "Totem-Pole Driven for High-Capacitance Loads", Colao et al., vol. 18, No. 11, 4/76.

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