Dual stress STI

Details Dual stress STI Dual stress STI

2011-04-19

2011-04-19

Vu, David (Department: 2829)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S257000, C438S198000, C438S199000, C257S369000, C257S315000

Reexamination Certificate

active

07927968

ABSTRACT:
The embodiments of the invention provide a device, method, etc. for a dual stress STI. A semiconductor device is provided having a substrate with a first transistor region and a second transistor region different than the first transistor region. The first transistor region comprises a PFET; and, the second transistor region comprises an NFET. Further, STI regions are provided in the substrate adjacent sides of and positioned between the first transistor region and the second transistor region, wherein the STI regions each comprise a compressive region, a compressive liner, a tensile region, and a tensile liner.

REFERENCES:
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patent: 6943391 (2005-09-01), Chi et al.
patent: 2004/0113174 (2004-06-01), Chidambarrao et al.
patent: 2005/0260806 (2005-11-01), Chang et al.
patent: 2006/0003510 (2006-01-01), Kammler et al.
patent: 2006/0022270 (2006-02-01), Boyd et al.
patent: 2006/0255415 (2006-11-01), Freeman et al.
patent: 2007/0096195 (2007-05-01), Hoentschel et al.
patent: 2007/0252214 (2007-11-01), Zhu et al.
patent: 150732 (2004-06-01), None

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