Dual stress memorization technique for CMOS application

Details Dual stress memorization technique for CMOS application Dual stress memorization technique for CMOS application

2011-06-28

2011-06-28

Ha, Nathan W (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Heterojunction device

Avalanche diode

C257SE21162

Reexamination Certificate

active

07968915

ABSTRACT:
A stress-transmitting dielectric layer is formed on the at least one PFET and the at least one NFET. A tensile stress generating film, such as a silicon nitride, is formed on the at least one NFET by blanket deposition and patterning. A compressive stress generating film, which may be a refractive metal nitride film, is formed on the at least one PFET by a blanket deposition and patterning. An encapsulating dielectric film is deposited over the compress stress generating film. The stress is transferred from both the tensile stress generating film and the compressive stress generating film into the underlying semiconductor structures. The magnitude of the transferred compressive stress from the refractory metal nitride film may be from about 5 GPa to about 20 GPa. The stress is memorized during an anneal and remains in the semiconductor devices after the stress generating films are removed.

REFERENCES:
patent: 7226834 (2007-06-01), Bu et al.
patent: 7511348 (2009-03-01), Ko et al.
patent: 2002/0020922 (2002-02-01), Yamada et al.
patent: 2005/0158937 (2005-07-01), Yang et al.
patent: 2007/0090395 (2007-04-01), Sebe et al.
patent: 2007/0105368 (2007-05-01), Tsui et al.
patent: 2007/0187770 (2007-08-01), Ahn et al.
patent: 2007/0202653 (2007-08-01), Hoentschel et al.
patent: 2007/0249069 (2007-10-01), Alvarez et al.
patent: 2008/0054415 (2008-03-01), Frohberg et al.
patent: 2008/0061285 (2008-03-01), Arghavani et al.
patent: 2008/0081480 (2008-04-01), Frohberg et al.
patent: 2008/0083955 (2008-04-01), Kanarsky et al.
patent: 2008/0099786 (2008-05-01), Maeda et al.
patent: 2008/0124855 (2008-05-01), Widodo et al.
patent: 2008/0169484 (2008-07-01), Chuang et al.
patent: 2008/0179661 (2008-07-01), Richter et al.
patent: 2008/0237734 (2008-10-01), Hung et al.
patent: 2008/0303062 (2008-12-01), Mimura et al.
patent: 1445838 (2003-10-01), None
patent: 1971882 (2007-05-01), None

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