Dual source side polysilicon select gate structure and...

Details Dual source side polysilicon select gate structure and... Dual source side polysilicon select gate structure and...

1999-09-30

2001-07-24

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185170, C365S185050, C365S185010, C365S185140

Reexamination Certificate

active

06266275

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of programmable non-volatile memory. Specifically, the present invention relates to the field of NAND-type floating gate flash memory cells which are programmed and erased using a high programming voltage.
2. Discussion of the Related Art
FIG. 1
illustrates a conventional NAND-type flash memory cell
100
suitable for use in the memory array. In the cell
100
, sixteen floating gate storage transistors
101
-
104
are connected in series to a bit line
105
which is used for reading and programming individual storage transistors within the cell. Each storage transistor
101
-
104
is equipped with a polysilicon floating gate
105
-
108
. The polysilicon floating gates
105
-
108
are “floating” in the sense that they are electrically isolated under normal conditions since they are surrounded by insulating layers, typically silicon dioxide, on all sides.
Specifically, each floating gate
105
-
108
is separated by its corresponding channel by a silicon dioxide layer
109
-
112
. The energy differential between the conduction band and the valence band in silicon is approximately 1.1 eV (electron-Volts). However, the energy differential between the conduction and the valence band in silicon dioxide is approximately 9 eV. Silicon dioxide's relatively large energy differential between the conduction band and the valence band is precisely the reason that silicon dioxide is generally non-conductive and is generally a very good insulator. An electron in an atomic or molecular orbit, thus within the valence band, must gain 9 eV of energy to break free of its orbit and enter the conduction band as a free charge carrier. When silicon and silicon-dioxide are joined, the conduction band of silicon dioxide is approximately 3.25 eV above the conduction band of silicon. Because an average electron possesses a thermal energy of only approximately 0.025 eV at room temperature, and because the variation in energy for individual electrons is not sufficiently high, the probability of an electron in the conduction band of silicon gaining enough energy to enter the conduction band in silicon dioxide is infinitesimally small. Although the 3.25 eV conduction band barrier always exists at a silicon to silicon-dioxide junction, the energy levels of electrons above and below the junction are directly affected by the potential gradient created by an electric field.
For example, a polysilicon gate overlies a silicon dioxide insulation layer which itself overlies a silicon transistor device channel. When a vertical electric field is applied in the silicon dioxide by raising the voltage of the polysilicon gate, the conduction band electrons in the silicon dioxide at some vertical distance above the channel to silicon dioxide junction will possess the same energy as the conduction band electrons in the underlying channel. As the strength of the field increases, the vertical distance decreases between the channel-oxide junction and the point at which silicon dioxide conduction band electrons possess only the same energy as silicon conduction band electrons. When this vertical distance becomes small enough due to a large enough electric field, a significant finite probability exists that an electron in the conduction band of the silicon channel will vertically “tunnel” from the channel to the conduction band of the oxide above the channel-oxide junction. After vertically tunneling into the conduction band of the oxide, the electron can proceed into the conduction band of the gate. The above-described electron tunneling phenomenon is called Fowler/Nordheim tunneling.
During programming of one of the storage transistors of the flash memory cell
100
, Fowler/Nordheim tunneling is used to tunnel electrons to one of the floating gates
105
-
108
from the corresponding device channel. During an erase operation, Fowler/Nordheim tunneling is used to tunnel electrons off the floating gates
105
-
108
and into the corresponding device channels
109
-
112
. The strength of an electric field is generally the voltage differential per unit distance. Therefore, in order to generate electric fields large enough for tunneling to occur without requiring excessively high voltages, the tunnel oxide
109
-
112
must be very thin.
FIG. 1
illustrates two NAND-type flash memory cells which share the same word lines wL
0
-wL
15
and select lines SG
1
and SG
2
. A flash memory array may be organized such that bit lines run vertically and are shared amongst a large number of cells. Word lines and select lines may run horizontally and may be shared by a large number of cells. Selecting one specific word line and one specific bit line uniquely identifies a specific storage transistor within the array. Each unique select line and bit line combination identifies a specific NAND flash memory cell having several storage transistors.
A typical program operation is performed using all bit lines of a selected word that has previously been erased such that all storage transistors included in the word contain ones. A program operation typically involves writing zeros into some of the bit line locations while inhibiting the writing of zeros into the remaining locations in which ones are to be stored.
For example, in the small section of an array illustrated in
FIG. 1
, the programming of the word corresponding to word line wL
1
will be discussed below. In this example, a zero is programmed into storage transistor
102
while a one remains stored in storage transistor
113
within NAND cell
114
. To effect this programming pattern the bit line BIT
0
105
is driven to zero volts while the bit line BIT
1
115
is driven to Vcc. The bit select gate line SG
1
is driven to Vcc, while the source select gate line SG
2
is driven to ground.
After the bit lines are set up, the word lines wL
0
-wL
15
are driven upward from zero volts. A storage transistor having a positive threshold voltage stores a zero, while a negative threshold voltage is indicative of a one. As the word lines wL
0
-L
15
rise, eventually all storage transistors
101
-
104
and
118
,
113
,
119
, and
120
are turned on regardless of whether or not a zero or a one is currently stored on any given storage transistor.
Under these conditions, the bit select transistor
116
of the NAND cell
100
to be programmed is turned on and it pulls the sources, drains, and channels of all the storage transistors
101
-
104
in NAND cell
100
to zero volts. Meanwhile, the bit select transistor
117
of the NAND cell
114
to be program inhibited raises the sources, drains, and channels of all the storage transistors
118
,
113
,
119
,
120
to Vcc−VtSG
1
, where VtSG
1
is the threshold voltage of the bit select gate
117
.
The unselected word lines wL
0
and wL
2
(not shown) through wL
15
are driven to about 10 Volts. The selected word line wL
1
is driven to the high programming voltage which may be as high as 20 Volts. After the channels of the program inhibited NAND string
114
are driven to Vcc−VtSG
1
, the bit select transistor
117
turns off, and the sources, drains, and channels of the storage transistors
118
,
113
,
119
,
120
of the program inhibited NAND cell
114
become a series of linked floating nodes. As the voltages on the control gates connected to the word lines wL
0
-wL
15
continue to rise after the bit select transistor
117
has turned off, the capacitive coupling between the control gate, the floating gate, and the channel cause the channel voltage to rise along with the control gate voltage. The capacitive coupling results from the fact that the negative plate, the channel, of the capacitance is electrically isolated when the bit select transistor
117
turns off. Because the voltage across an ideal capacitance with one terminal open circuited cannot change, the raising of voltage of the positive plate also raises the voltage of the negative plate. The control gate is the positive plate of the capacitor, and the channel is the negative plate.

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