Dual-slope waveform generation circuit

Details Dual-slope waveform generation circuit Dual-slope waveform generation circuit

1988-09-16

1990-01-16

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307451, 307279, H03K 512, H03K 1716

Patent

active

048945609

ABSTRACT:
A dual-slope waveform generation circuit without a DC path and with decreased layout area including a pull-up and pull-down resistor, a transmission gate and an inverter. An input signal IN is applied to the pull-up transistor, to each gates of MOS transistors M.sub.1, M.sub.2 composing of the inverter A, and to drains of MOS transistors M.sub.3, M.sub.4 composing of the transmission gate B. A common node in the inverter is connected to the gate of the N type MOS transistor in the transmission gate. The sources of the transistors M.sub.3, M.sub.4 are connected to the gate of the pull-down transistor. An output signal OUT is applied to the gate of the transistor M.sub.4 and the signal is fed back.

REFERENCES:
patent: 4543494 (1985-09-01), Wakimoto
patent: 4571504 (1986-02-01), Iwamoto et al.

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