Dual-slope analog-to-digital converter and comparison circuit

Details Dual-slope analog-to-digital converter and comparison circuit Dual-slope analog-to-digital converter and comparison circuit

2002-08-30

2003-11-11

Williams, Howard L. (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S128000

Reexamination Certificate

active

06646586

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a dual-slope analog-to-digital converter and a comparison circuit. In particular, the present invention relates to a dual-slope analog-to-digital converter with a comparison circuit for reduction of rollover error due to various input signals in various conditions influenced by different procedures and environments.
2. Description of the Related Art
FIG. 1
shows a block diagram of a conventional dual-slope ADC. In
FIG. 1
, the dual-slope ADC comprises a buffer
102
, an integrator
104
, a comparator
106
, a resistance
108
, and capacitances
110
and
112
. The integrator
104
, resistance
108
, and capacitances
110
compose an integration circuit. An integration voltage V
INT
(not shown in
FIG. 1
) is input into the dual-slope ADC through input terminals IN
1
, and IN
2
. The integration voltage V
INT
passes through the buffer
102
to the integrator
104
for a fixed amount of time to store charge in the capacitor
110
. The dual-slope ADC is fed with an opposite polarity voltage V
DINT
to effect de-integration. When the output voltage V
IO
of the integrator
104
returns to the initial point, called zero crossing, the comparator
106
changes its state and stops de-integration. The output voltage of the comparator
106
in
FIG. 1
is V
CMP
. If the integration time is T
INT
, the de-integration time T
DINT
is related to the T
INT
as follows:
|
V
INT
|×T
INT
=|V
DINT
|×T
DINT
  (1)
Conventional dual-slope ADC has single output of the comparator
106
. In the following, two situations are considered. In one, the integration voltage V
INT
input into the dual-slope ADC is positive. In the other, the integration voltage V
INT
input into the dual-slope ADC is negative.
FIG. 2
a
shows the relation between the output voltage of the integrator V
IO
and the output voltage of the compactor V
CMP
when the input voltage is positive. In
FIG. 2
a
, line 22 shows the relation between the output voltage of the integrator V
IO
and time. Line
24
shows the relation between the output voltage of the compactor V
CMP
and time. A voltage V
IN2
in the input terminal IN
2
is an initial voltage, i.e. the output voltage V
IO
equaling the voltage V
IN2
is called zero crossing. When the positive integration voltage V
INT
input into the dual-slope ADC, i.e. the voltage input to the input terminal IN
1
is higher than the voltage input to the input terminal IN
2
, while the output voltage V
IO
is equal to the voltage V
IN2
(referring to t
1
in
FIG. 2
a
), the output voltage of the integrator V
IO
changes from a negative (low) voltage to a positive (high) voltage and the output voltage of the compactor V
CMP
is also from a negative (low) voltage to a positive (high) voltage. Thus, a P-channel metal oxide semiconductor (PMOS) in the output stage of the comparator changes from “OFF” to “ON” status and a N-channel metal oxide semiconductor (NMOS) in the output stage of the comparator changes from “ON” to “OFF” status.
FIG. 2
b
shows the relation between the output voltage of the integrator V
IO
and the output voltage of the compactor V
CMP
when the input voltage is negative. In
FIG. 2
b
, line
26
shows the relation between the output voltage of the integrator V
IO
and time. Line
28
shows the relation between the output voltage of the compactor V
CMP
and time. A voltage V
IN2
in the input terminal IN
2
is an initial voltage, i.e. the output voltage V
IO
equaling the voltage V
IN2
is called zero crossing. When the negative integration voltage V
INT
input into the dual-slope ADC, i.e. the voltage input to the input terminal IN
1
, is lower than the voltage input to the input terminal IN
2
, while the output voltage V
IO
is equal to the voltage V
IN2
(referring to t
2
in
FIG. 2
b
), the output voltage of the integrator V
IO
changes from a positive (high) voltage to a negative (low) voltage and the output voltage of the compactor V
CMP
is also from a positive (high) voltage to a negative (low) voltage. Thus, a P-channel metal oxide semiconductor (PMOS) in the output stage of the comparator changes from “ON” to “OFF” status and a N-channel metal oxide semiconductor (NMOS) in the output stage of the comparator changes from “OFF” to “ON” status.
The measured result of the dual-slope ADC is influenced by the time of the change of the output voltage of the compactor V
CMP
. The time of the change of the output voltage of the compactor V
CMP
is influenced by the delay of the comparator. In some applications with higher conversion rate, a slight delay may result in measured result errors. In the prior art, zero calibration is provided to resolve the above problem. However, in the above two situations, the delay of the comparator is different. In the situation shown in
FIG. 2
a
, the state of the comparator is changed by PMOS. In the situation shown in FIG.
2
b
, the state of the comparator is changed by NMOS. Thus, the different delay cannot be compensated for by the zero calibration. The different delay also increases rollover errors in the dual-slope ADC, i.e. when two voltages with the same value but opposite polarity are input, measured result errors may increase. Furthermore, rollover errors may increase with different procedures and environments.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a dual-slope analog-to-digital converter and a comparison circuit for the dual-slope analog-to-digital converter to reduce rollover errors due to various input signals in various conditions influenced by different procedures and environments.
In the invention, the dual-slope analog-to-digital converter comprises a buffer, an integrator coupled to the buffer, and a comparison circuit. The comparison circuit comprises a differential output comparator and a comparison unit. The differential output comparator is coupled to the integrator and produces a pair of differential signals to output. The comparison unit receives the differential signals and chooses a signal, whose voltage is from a first level to a second level, from the differential signals to produce an output signal.
Furthermore, the invention provides a kind of comparison circuit for the dual-slope analog-to-digital converter. The dual-slope analog-to-digital converter comprises a buffer and an integrator coupled to the buffer. The comparison circuit comprises a differential output comparator and a pair of single output comparators. The differential output comparator is coupled to the integrator and produces a pair of differential signals to output. Each of the single output comparators receives one of the differential signals to choose a signal whose voltage is from a first level to a second level from the differential signal. An output signal is produced by the single output comparator that receives the signal whose voltage changes from the first level to the second level.
The invention also provides another kind of comparison circuit for a dual-slope analog-to-digital converter. The dual-slope analog-to-digital converter comprises a buffer and an integrator coupled to the buffer. The comparison circuit comprises a differential output comparator, a multiplexer and a single output comparators. The differential output comparator is coupled to the integrator and produces a pair of differential signals to output. The multiplexer receives the differential signals and chooses a signal whose voltage is from a first level to a second level from the differential signals. The single output comparator receives the signal whose voltage changes from the first level to the second level to produce an output signal.


REFERENCES:
patent: 4254406 (1981-03-01), Meares
patent: 4633223 (1986-12-01), Senderowicz
patent: 5229772 (1993-07-01), Hanlon
patent: 5373292 (1994-12-01), Yasuda
patent: 5592168 (1997-01-01), Liao

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