Dual silicon chip package

Details Dual silicon chip package Dual silicon chip package

1999-03-04

2001-09-18

Wilczewski, Mary (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

For plural devices

C257S777000

Reexamination Certificate

active

06291881

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a semiconductor package required for forming the package. More particularly, the present invention relates to a dual silicon chip package.
2. Description of Related Art
The manufacturing of an integrated circuit (IC) can be roughly divided into three separate stages: the manufacturing of a silicon chip, the production of an integrated circuit on silicon chip, and the packaging of the silicon chip. Hence, the packaging of the silicon chip can be regarded as the final stage in the integrated circuit fabrication process. Conventional IC package used to contain a single chip. However, in order to increase the capacity of, say, a memory package, or to integrate silicon chips having different functions, a number of packages now contain two silicon chips.
In general, for an IC package having two silicon chips, the silicon chips are respectively mounted on the upper side and the lower side of the lead frame. However, if the circuit layout of the two silicon chips is the same, for example, two pieces of identical DRAM chips are used to increase memory capacity, the metal wires that connect the bonding pads on the silicon chips with the lead frame may have to cross over each other, leading to certain degree of entanglement with each other. Therefore, various IC packaging methods are developed to prevent metal wires from crossing and entangling each other.
FIG. 1
is a schematic, cross-sectional side view of a conventional dual silicon chip package. As shown in
FIG. 1
, a first silicon chip
12
and a second silicon chip
16
are respectively mounted onto the upper and the lower surface of a die pad
14
. The lower silicon chip
16
has a circuit layout that is the same as the mirror image of the upper silicon chip
12
. Hence, locations of bonding pads on the lower silicon chip
16
are a mirror reflection of the locations of bonding pads on the upper silicon chip
12
. This type of IC package ensures that no metallic wires
10
cross each other. However, due to the mirror reflection layout of silicon chip
16
with respect to the silicon chip
12
, circuit design between the two must be different. Hence, an IC package that employs this type of packaging requires two functionally the same silicon chip having different circuit layout. Thus, besides increasing production cost, this type of design increases production time as well.
FIG. 2
is a schematic, cross-sectional side view of another conventional dual silicon chip package. As shown in
FIG. 2
, interposers
26
are added to the underside of the die pad
23
. Through these interposers
26
, bonding pad positions of the lower silicon chip
24
can be switched. Therefore, the bonding pad positions of the lower silicon chip
24
with respect to the surrounding leads corresponds to the bonding pad positions of the upper silicon chip
22
. With this type of arrangement, no metallic wires
20
have to cross each other. However, if the lower silicon chip
24
is of a considerable size, the underside of the die pad
23
may not have sufficient area to accommodate the interposers
26
. Furthermore, using interposers
26
increases the interface between the upper silicon chip
22
and the lower silicon chip
24
. As interface increases, problems caused by stress and heat increases correspondingly. All these factors contribute to a lower reliability of the package and compromise the operation speed of the chip.
An alternative structure, very similar to the dual silicon chip package but using a printed circuit board (PCB) instead of a silicon die pad, is also quite common. Since a printed circuit board is employed, the upper silicon chip is able to match bonding pad positions with respect to the lower silicon chips. However, material for fabricating PCB is quite different from the die pad in a lead frame. Hence, adhesive strength with a silicon chip is inferior and cost of production is consequently higher. In addition, an electrical signal has to go through the PCB, which can lead to signal degradation problems.
All the aforementioned IC packages for housing two silicon chips rely on the die pad as a supporting structure. These type of structures, however, tend to require considerable interface areas. Moreover, stress resulting from the use of different materials also lowers the reliability of the device. Furthermore, since the silicon chips are attached to the die pad with metal wires connecting to the lead frame, the only way for heat to dissipate is through those wires. Insufficient heat dissipation can easily lead to an increase in resistance and a decrease in operating speed for the device inside the package.
In light of the foregoing, there is a need to improve the design of the dual silicon chip IC package.
SUMMARY OF THE INVENTION
Accordingly, the purpose of the present invention is to provide a package structure for accommodating two silicon chips.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a dual silicon chip package structure. The package includes a lead frame, a first silicon chip and a second silicon chip. The front face of the first silicon chip has a plurality of bonding pads distributed around its periphery. The back face of the first silicon chip is attached to the leads of the lead frame. The second silicon chip is smaller than the first silicon chip, and hence the backside of the second silicon chip can be attached to the front face of the first silicon chip. There is a plurality of conductive wires linking the bonding pads on the first silicon chip to the upper side of the lead frame. Similarly, there is a plurality of conductive wires linking the bonding pads on the second silicon chip and the upper side of the lead frame. Because the first and the second silicon chips form a stack, the conductive wires do not cross-entangle or cross-connect with each other.
The present invention also provides a second embodiment of the dual silicon chip package structure. The package includes a lead frame, a first silicon chip and a second silicon chip. The first silicon chip and the second silicon chip have roughly the same size. The front face of the first silicon chip has a plurality of first bonding pads distributed near its central region while the peripheral region are attached to the lead frame. Meanwhile, the backside of the second silicon chip is attached to the backside of the first silicon chip. A plurality of conductive wires is used for connecting the bonding pads on the first silicon chip to the lower side of the lead frame. Similarly, a plurality of conductive wires also connects the bonding pads on the second silicon chip to the upper side of the lead frame. Hence, conductive wires do not cross-entangle and cross-connect with each other.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5530292 (1996-06-01), Waki et al.
patent: 5545922 (1996-08-01), Golwalker et al.
patent: 5793108 (1998-08-01), Nakanishi et al.
patent: 5917242 (1999-06-01), Ball
patent: 5952725 (1999-09-01), Ball
patent: 5959347 (1999-09-01), Grigg et al.
patent: 6002178 (1999-12-01), Lin

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