Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Bipolar transistor
Reexamination Certificate
2001-04-19
2003-03-11
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Bipolar transistor
C257S198000
Reexamination Certificate
active
06531720
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention generally relates to the fabrication of semiconductor electronic integrated circuits, and more particularly to a method for making a self-aligned heterojunction bipolar transistor (HBT).
2. Description of the Related Art
The bipolar transistor is a basic element in integrated circuits because of its high-speed switching capability and current carrying capacity. One type of bipolar transistor, known as a heterojunction bipolar transistor (HBT), offers advantages over conventional junction bipolar transistors by providing a bandgap difference between base and emitter regions. In an NPN transistor, this bandgap difference restricts hole flow from base to emitter which, in turn, improves emitter-injection efficiency and current gain. The improved emitter-injection efficiency allows for the use of low resistivity base regions and high resistivity emitter regions. This creates fast devices without compromising other device parameters. As a result, HBTs realize high current gain while simultaneously having a low base resistivity and low emitter base junction capacitance.
Attempts have been made to improve the performance of SiGe HBT transistors. One method uses low-temperature, high-quality homo or heterojunction epitaxial techniques to achieve emitter-base-collector profile optimization. Other methods scale the base width and emitter-base-collector doping profiles of the transistor. While these methods have achieved modest gains in transistor performance, all of them have proven ineffective for reducing parasitic resistances and capacitances such as extrinsic base resistance and collector-base/collector-substrate capacitances.
One conventional approach which attempts to reduce the base-emitter and base-collector junction capacitances and base resistance is disclosed in U.S. Pat. No. 4,499,657. In this patent, a lightly doped silicon layer is epitaxially grown on an oxide film with openings disposed on one main face of a silicon substrate. Single crystal portions are formed in the openings and polycrystalline portions over the oxide. Ion implantation and thermal annealing are then used to convert the polycrystalline portions to opposite conductivity type external base regions and opposite conductivity internal base regions are formed in the single-crystal portions. Finally, arsenic ions are implanted into the internal base to form n-conductivity type emitter regions.
The approach taken in the '657 patent is disadvantageous in a number of respects. First, this method depends on the different rates of dopant diffusion in single-crystal and polycrystalline semiconductor material to form intrinsic and extrinsic base regions. Under these circumstances, it is difficult to control the formation of a thin intrinsic base region in which emitter regions must ultimately be formed. Also, this method produces emitter and base regions which are not self-aligned. This inevitably results in lateral displacement between the emitter and collector, which negatively impacts the performance of the transistor. As a result, this approach is unsuitable for achieving the fine control required when forming an emitter in the intrinsic base region.
U.S. Pat. No. 5,117,271 discloses another conventional method for reducing parasitic resistances and capacitances in an HBT device. In this patent, the extrinsic base region is scaled using spacers formed on the sides of an emitter pedestal. A summary of this method is provided below with reference to
FIGS. 8 and 9
.
As shown in
FIG. 8
, the method begins by forming a structure which includes an n
+
collector region
1
on top of a sub-collector layer (not shown). In a layer
2
above the collector region, an intrinsic base region
3
of p-type conductivity is formed by depositing an in-situ p-type doped SiGe layer. The intrinsic base region is covered by three layers, namely a silicon dioxide layer
4
, a silicon nitride layer
5
, and a polysilicon layer
6
. An emitter pedestal structure consisting of a nitride layer
7
and an oxide layer
8
are then formed on the polysilicon layer.
In subsequent steps, extrinsic (p
+
) base regions
9
are formed through ion implantation using boron as the dopant impurity. The extrinsic base regions are scaled and self-aligned using spacers
10
formed on the sides of the emitter pedestal. The emitter pedestal oxide and spacer oxide are then removed. With the pedestal nitride
7
in place, the polysilicon
6
is converted into oxide everywhere except directly underneath the pedestal nitride. Subsequently, the pedestal nitride is removed, and an opening is formed in polysilicon and nitride layers
6
and
5
. Before oxide layer
4
is opened, an additional n-type dopant is implanted through this opening to link up with the existing n
+
collector region, and this implant is self-aligned to the emitter. After layer
4
is removed, the emitter opening
10
as shown in
FIG. 9
is filled with material of n
+
conductivity which corresponds to the emitter
11
of the transistor. A silicon nitride
12
cap layer is then formed over the emitter. Subsequently, a thermal drive-in will drive in a thin n
+
region which is the single-crystalline emitter region
22
.
The conventional method described above is disadvantageous because it cannot optimize transistor performance. It is noted that the thickness of the sidewall spacers sets the distance between the edge of the extrinsic base implants and the edge of the active bipolar device. Consequently, in the structure shown in the '271 patent, if the extrinsic base sidewall is reduced too much, the base resistance underneath the sidewall (R
b,sw
) will experience a reduction, but the collector-to-extrinsic base capacitance (C
cb,ext
) will increase and f
max
(i.e., the power gain bandwidth product for the device, or the frequency at which the power gain has dropped to a value of 1) will be lowered. This has the following effect.
RF applications generally operate at frequencies up to some fraction of f
max
(typically ¼-½0 f
max
), so a higher f
max
is desirable to allow the device to be useful in higher frequency applications. Higher peak f
max
at a given current also can be traded off during circuit design for the same f
max
but at a lower current, allowing for a lower power design. In the structure shown in the '271 patent, if the extrinsic base sidewall is reduced too much, f
max
will become lowered thereby compromising device performance.
A reduction in the extrinsic base sidewall thickness in the '271 patent also produces a significant drop off in Early Voltage. Early voltage is a measure of the flatness of an I
c
to V
ce
curve. A flatter I
c
vs. V
ce
curve produces a higher Early Voltage, which is more ideal because of the potential for higher maximum voltage gain. On the other hand, a more slopped the I
c
vs. V
ce
curve limits the maximum voltage gain that the device can achieve. By reducing the sidewall in the '271 patent, Early Voltage is reduced in a manner which significantly degrades device performance.
If the extrinsic base sidewall thickness is increased, the extrinsic base will be formed far away from the collector, which will result in a reduction of collector-to-extrinsic base capacitance C
cb,ext
. This, however, will also bring the extrinsic base away from the emitter, which has the undesirable effect of increasing the resistance underneath the sidewall R
b,sw
and lowering f
max
. It is therefore apparent that a trade-off exists between collector-to-extrinsic base capacitance C
cb,ext
and the resistance underneath the sidewall R
b,sw
The scaling approach taken by the '271 patent is limited because only one of R
b,sw
and C
cb,ext
can be improved at the expense of the other.
In view of the foregoing considerations, it is apparent that there is a need for an improved method for forming a heterojunction bipolar transistor which employs a scaling approach that reduces both collector-to-extrinsic base capacitance C
cb,ext
Freeman Gregory G.
Greenberg David R.
Jeng Shwu-Jen
International Business Machines - Corporation
Meier Stephen D.
Whitham Curtis & Christofferson, P.C.
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