Dual serial-parallel-serial analog memory

Details Dual serial-parallel-serial analog memory Dual serial-parallel-serial analog memory

1974-11-27

1976-04-27

Fears, Terrell W.

Communications: electrical

Digital comparator systems

307221C, 307222C, 307238, 340174SR, G11C 1140

Patent

active

039538370

ABSTRACT:
A CCD shift register involves a serial input channel and a serial output channel interconnected by a plurality of parallel channels formed in a semiconductor body with separate arrays of multi electrode sets of phase electrodes overlying the input, parallel and output channels. A summing gate electrode common to all of the parallel channels is adjacent the output channel. Control means actuates the gate to transfer charge packets from each parallel channel into the output channel and clocks the charge packets to the output. Two such shift registers are provided with means to inject time samples of an input signal alternately to the two shift registers and to multiplex the outputs therefrom.

REFERENCES:
patent: 3643106 (1972-02-01), Berwin
patent: 3763480 (1973-10-01), Weimer
patent: 3797002 (1974-03-01), Brown

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