Dual sequencer microprocessor

Details Dual sequencer microprocessor Dual sequencer microprocessor

1978-11-02

1982-03-16

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 922, G06F 938

Patent

active

043204538

ABSTRACT:
A control section consisting of an address processing circuit and two sequencers for use in a programmable microprocessor. The address processing circuit has two sets of input lines and one set of output lines, and is adapted to convert address information provided at the input lines into a signal at the output lines which consists of microinstructions suitable for use in other portions of the microprocessor. Each sequencer is connected to one set of input lines of the address processing circuit and is adapted to receive data from an external source and provide address information corresponding to such data to the address processing circuit. In operation, the signal provided at the output lines of the address processing circuit consists of time-division multiplexed microinstructions, each such microinstruction being derived from one of the two external sources. The utilization of two sequencers in the control section of the present device and the corresponding time-division multiplexed microinstructions enables a microprocessor which utilizes the control section of the present invention to simultaneously control two realtime tasks.

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Leininger, J. C. et al., "Conditional Control Store Latch Freeze", IBM Tech. Discl. Bull., vol. 20, No. 3, Aug. 1977, pp. 881-882.

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