Dual selection system for reference frequency for use in a clock

Details Dual selection system for reference frequency for use in a clock Dual selection system for reference frequency for use in a clock

1991-07-29

1993-06-08

Richardson, Robert L.

Boots, shoes, and leggings

36470507, 368159, 368200, G06F 106

Patent

active

052186946

ABSTRACT:
A dual selection system for a reference frequency for use in a clock comprising a microcomputer for controlling the whole system and outputting a switching signal and frequency-demultiplying signals. A system oscillator produces an oscillation signal of 4.194304 MHz. A system frequency-demultiplier for frequency-dividing an output of a first buffer to apply a system clock signal to the microcomputer. A clock oscillator produces an oscillation signal of 32.768 KHz, and a clock frequency-demultiplier for frequency-dividing an output of a second buffer applies a clock signal of 1 Hz for clock to the microcomputer.
When an option is selected, a system oscillation signal of 4.194304 MHz is selected and frequency-demultiplied by 2.sup.22 to a clock signal of 1 Hz for a clock. When that the option is not selected, the clock oscillation signal of 32.768 KHz is frequency-divided by 2.sup.15 to a clock signal of 1 Hz for the clock.

REFERENCES:
patent: 4342092 (1982-07-01), Kumagi

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