Dual return-to-zero pulse encoding in a DAC output stage

Details Dual return-to-zero pulse encoding in a DAC output stage Dual return-to-zero pulse encoding in a DAC output stage

1997-09-25

2000-05-09

Hoff, Marc S.

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

341152, H03M 166

Patent

active

060610107

ABSTRACT:
In an output stage for a DAC, such as an oversampled DAC, an apparatus and method which generates, for each bit clock period and for each bit to be converted, two or more (not just one) return-to-zero (RTZ) signals. The RTZ signals are delayed from the other (if two RTZ signals are employed, they are delayed by one-half clock cycle relative to each other). The two RTZ signals are summed to yield the DAC output from said bit.

REFERENCES:
patent: 4772871 (1988-09-01), Suzuki et al.
patent: 4947171 (1990-08-01), Pfeifer et al.
patent: 5528239 (1996-06-01), Swanson et al.
patent: 5610606 (1997-03-01), Fukunaga et al.
patent: 5719572 (1998-02-01), Gong

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