Boots – shoes – and leggings
Patent
1983-07-20
1985-07-16
Shaw, Gareth D.
Boots, shoes, and leggings
G06F 928, G06F 926
Patent
active
045300470
ABSTRACT:
An electronic digital dual processor system including an interface to an external memory in addition to an internal memory. The dual processor architecture includes dual independent and simultaneously operable registers for the temporary storage of data from an arithmetic and logic unit and for memory addressing. The internal memory includes a ROM for storing instructions and a RAM for storing data. The internal memory is also used to store instructions. Control and timing circuitry is included for the generation of microinstructions for the instructions stored in the memory. The control and timing circuitry provide for the simultaneous and independent execution of the microinstructions involving the dual register sets.
REFERENCES:
Micromultiprocessing: An Approach to Multiprocessing at the Level of Very Small Tasks, J. L. Rosenfeld and Raymond D. Villani, I.E.E.E. Transactions on Computers, vol. C-12, No. 2, Feb. 1973, pp. 149-153.
Developing a Multiple-Instruction-Stream Single-Chip Processor, W. J. Kaminsky and E. S. Davidson, Computer, vol. 12, No. 12, Dec. 1979, pp. 66-76.
Brown Sammy K.
Koeppen Peter L.
Rogers Gerald D.
Solimeno Duane
Dorsey Daniel K.
Heiting Leo N.
Sharp Melvin
Shaw Gareth D.
Texas Instruments Incorporated
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