Dual-reference delay-locked loop (DLL)

Details Dual-reference delay-locked loop (DLL) Dual-reference delay-locked loop (DLL)

2011-05-03

2011-05-03

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S149000

Reexamination Certificate

active

07936194

ABSTRACT:
Embodiments of the present invention are directed to a dual-reference delay-locked loop that includes a first delay element that delays a clock signal. The rising phase and the falling phase of the delayed clock signal are used as a first and a second reference phases, respectively, for a phase detector. A second delay element delays the first reference signal with a tracking phase that centers between the two reference phases. The phase detector detects a difference between the average of the reference phases and the tracking or resultant phase and outputs a difference signal that biases the delay elements to slew to the left or the right so that the resultant phase is centered between the reference phases corresponding to the rising and falling edges of the incoming clock.

REFERENCES:
patent: 5670903 (1997-09-01), Mizuno
patent: 7019573 (2006-03-01), Matsuno
patent: 7081782 (2006-07-01), Kizer et al.

Affiliated with

Also associated with

Rating

Dual-reference delay-locked loop (DLL) does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dual-reference delay-locked loop (DLL), we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual-reference delay-locked loop (DLL) will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2633566