Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-04-19
2004-02-03
Mai, Son (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185200
Reexamination Certificate
active
06687162
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to nonvolatile semiconductor memory, and more specifically to techniques for reading data from split-gate type of nonvolatile semiconductor memory cells using multiple reference cells.
The purpose of storing data into a memory cell is so that at some later time the data can be read back again. During a read operation, the bit in the memory cell is determined to be equal to a logic high (“1”) or a logic low (“0”). This is typically accomplished by comparing a value (e.g., a current) for a data cell being read with a reference value of a known cell, which is often referred to as a reference cell. The data value stored in the data cell is determined to be a logic high if the value of the data cell is higher than the reference value of the reference cell, and a logic zero otherwise.
A reference cell is typically designed to have a structure very similar to that of the data cells in the memory array. This design allows the characteristics of the reference cell to match those of the data cells over process variations during fabrication. This design further allows the reference cell to track the data cells over temperature and power supply variations during normal use.
The use of a single reference cell for read operation may not provide high performance for certain memory designs. For example, for a split-gate type of nonvolatile memory, the data cells are arranged in pairs and the first data cell in each pair may behave differently from the second data cell in the pair. The first and second data cells in each pair may be arranged (i.e., laid out) as mirror image of one another. Because of this mirrored arrangement, manufacturing imperfections (e.g., mask misalignment) can result in differences in the physical layouts between the first and second cells in the pair. The physical differences may then result in different electrical characteristics for the first and second cells in the pair.
For the split-gate type nonvolatile memory design, if the reference cell is implemented similar to the first cell, then it may match the process variations and track the temperature changes of all first cells very well. However, the matching and tracking may be poor for the second cells. As a result, performance will likely degrade if the reference cell is used to determine the data stored in the second cells.
As can be seen, techniques to accurately read data from split-gate type memory cells potentially having different characteristics are highly desirable.
SUMMARY OF THE INVENTION
The invention provides techniques to more accurately read values stored in data cells. In an aspect, multiple reference cells are used to provide reference values for reading data cells. One reference cell is provided for each group of data cells having similar configuration (e.g., similar layout and orientation). For split-gate memory cells, two reference cells may be used, with one reference cell being used for a first set of memory cells having a first configuration and another reference cell being used for a second set of memory cells having a second configuration (which may be a mirrored image of the first configuration). In general, any number of reference cells may be used to provide reference values for any number of different memory cell configurations.
In another aspect, techniques are provided to better match the data paths for the reference and data cells for read operation. The values provided by the reference and data cells are typically amplified by respective sense amplifiers and then compared by a comparator. Any mismatch between the two data paths for the values from the data and reference cells may distort the values received at the comparator, and may result in erroneous detection.
The two data paths for the data and reference values may thus be matched. This matching may be achieved by (1) using the same circuit design for the data and reference sense amplifiers, (2) using the same layout and orientation for the sense amplifiers, (3) matching the lines for the two data paths, (4) matching the poly-silicon structure (e.g., length and width) and the diffusion region (e.g., doping concentration and contact) for the sense amplifiers and lines, and so on.
Various other aspects, embodiments, and features of the invention are also provided, as described in further detail below.
REFERENCES:
patent: 5717632 (1998-02-01), Richart et al.
patent: 6317362 (2001-11-01), Nomura et al.
patent: 6411549 (2002-06-01), Pathak et al.
Hoang Loc Bao
Hsueh Sheng-Hsiung
Kordesch Albert V.
Lee Ganshu Ben
Liu Chun-Mail
Dinh & Associates
Mai Son
Winbond Electronics Corporation
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