Dual receiver edge-triggered digital signal level detection syst

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307409, 307445, 365193, H03K 1901

Patent

active

053471849

ABSTRACT:
Two separate receivers (120,122) receive the input signal (128) and the clock signal (126). During the inactive state of the clock signal, the first receiver produces a low state output (130) and the second receiver produces a high state output (132). Both outputs feed combinational logic (124), which produces two outputs (142,144) both normally low. Upon transition of the clock signal, the output of only one of the receivers changes state to match the logic state of the input signal. The output of the other receiver maintains its logic state. Upon the change in the clock signal, only one of the combinational logic outputs changes state to a logical high state to indicate the state of the one input signal.

REFERENCES:
patent: 4719629 (1988-01-01), Wang
patent: 4900949 (1990-02-01), Saitoh
patent: 5083049 (1992-01-01), Kagey
patent: 5111433 (1992-05-01), Miyamoto

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