Dual rail processors with error checking on I/O reads

Details Dual rail processors with error checking on I/O reads Dual rail processors with error checking on I/O reads

1989-05-25

1993-09-28

Beausoliel, Jr., Robert W.

Excavating

371 683, 371 91, 364187, 3642681, 364DIG1, 36494392, 3649442, 364DIG2, G06F 1116, H04L 122

Patent

active

052491870

ABSTRACT:
A dual processor data processing system having interprocessor error checking includes a first central processing unit executing a series of instructions. A second central processing unit executes the same series of instructions independently of and in synchronism with the first central processing unit. A first data bus is coupled to the first central processing unit for receiving data to be input to the first central processing unit and a second data bus is coupled to the second central processing unit for receiving data to be input to the second central processing unit. Error checking devices are coupled to the first and second data busses for checking data transmitted over the first and second data busses and for detecting errors on I/O reads prior to delivery of the data to the first and second central processing units. The error checking devices include comparison means for indicating an error when the data on the first and second data busses are unequal. Error isolation devices are responsive to an error detected from the error checking means for analyzing the cause of error while maintaining system synchronization.

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