Dual-rail processor with error checking at single rail interface

Details Dual-rail processor with error checking at single rail interface Dual-rail processor with error checking at single rail interface

1987-09-04

1990-03-06

Fleming, Michael R.

Excavating

371 8, 364900, G06F 1120

Patent

active

049072285

ABSTRACT:
A dual processor computer system with error checking includes a first processing system for executing a series of instructions including output instructions. A second processing system executes the series of instructions independently of and in synchronism with the first processing system. Shared resource devices are coupled to the first and second processing systems for receiving data from output instructions from the first and second processing systems substantially simultaneously. Error checking devices are located downstream of the shared resource means for checking the data received from the first and second processing systems only following a write operation into the shared resource means.

REFERENCES:
patent: 3665173 (1972-05-01), Bouricius et al.
patent: 4009241 (1978-07-01), Ossfeldt
patent: 4012717 (1977-03-01), Censier
patent: 4030074 (1977-06-01), Giorcelli
patent: 4031372 (1977-06-01), Davis
patent: 4099234 (1978-07-01), Woods
patent: 4141066 (1979-02-01), Keiles
patent: 4153319 (1979-05-01), Plyler
patent: 4200226 (1980-04-01), Piras
patent: 4228496 (1980-10-01), Katzman et al.
patent: 4245344 (1981-01-01), Richter
patent: 4251873 (1981-02-01), Joby
patent: 4253147 (1981-02-01), MacDougall et al.
patent: 4350225 (1982-09-01), Sakata
patent: 4356546 (1982-10-01), Whiteside et al.
patent: 4371754 (1983-02-01), De
patent: 4400792 (1983-08-01), Strelow
patent: 4453215 (1984-06-01), Reid
patent: 4486826 (1984-12-01), Wolff et al.
patent: 4541094 (1985-09-01), Stiffler
patent: 4610013 (1986-09-01), Long
patent: 4654857 (1987-03-01), Samson
patent: 4751702 (1988-06-01), Beier
Chester, "Fault-Tolerant Computers Mature", Systems & Software, pp. 117-129 (Mar., 1985).
Depledge, et al., "Fault-Tolerant Microcomputer Systems for Aircraft", IERE Conference Proceedings 36, 1977, Proc. Conf. on Computer Systems & Technology Engineering, pp. 205-220 (Mar., 1977).
Beck, et al., "Implementation Issues in Clock Synchronization", Mar. 15, 1986 Draft (origin unknown).
Datapro Research Corporation, Feature Report (Dec. 1985), MO7-100-318 to MO7-100-323.
The Evolution of Fault-Tolerant Computing, Proceedings of the 1-Day Symposium on the Evolution of Fault-Tolerant Computing, Ed. by A. Avizienis, H. Kopetz, and J. Laprie (Jun. 30, 1986).
IBM System/88, The Operating System Reference, Jul., 1985.
Harrison, "S/88 Architecture and Design; S/88 Internals", Share 67 (8/12/86).
"System/88 Technical Overview" (date believed to be 2/86).
Tandem NonStop Computers, Datapro Research Corporation, Computers M11-822-101 to M11-822-119 (Oct., 1986).
Bartlett, "The Tandem Concept of Fault-Tolerance", (view 1985), M07-100-318 to M07-100-323.
Bernstein, "Sequoia: A Fault-Tolerant Tightly-Coupled Computer for Transaction Processing", Technical Report TR-85-03, pp. 1-43 (May 2, 1985).
Sequoia Technical Overview (date unknown but believed to be Mar., 1985 by virtue of annotation at the bottom of last page of this material).
Sequoia Hardware Architecture (1984).
Bernstein, Sequoia, Wang Institute of Graduate Studies (date unknown).
"How Technology is Cutting Fault-Tolerance Costs", Electronics 55-58 (Jan. 13, 1986).
Katsuki, et al., "Pluribus-An Operational Fault-Tolerant Multiprocessor", Proceedings of the IEEE, vol. 66, No. 10, (Oct., 1978).
Reynolds, "Architectures for Fault-Tolerant Spacecraft Computers", Proceedings of the IEEE, vol. 66, No. 10, pp. 1255-1268 (Oct., 1978).
Parallel 300 (1984).
Inselberq, "Multiprocessor Architecture Ensures Fault-Tolerant Transaction Processing", Many MicroSystems (Apr. 1983).
Anita Borq, "Targon/Nixdorf" (date unknown).
Losq, "A Highly Efficient Redundancy Scheme: Self-Purging Redundancy", IEEE Transactions on Computers, vol. C-25, No. 6 (Jun., 1986).
Su, et al., "A Hardware Redundancy Reconfiguration Scheme for Tolerating Multiple Module Failures", IEEE Transactions on Computers, vol. C-29, No. 3, (Mar., 1980).
Takaoka, et al., "N-Fail-Safe Logical Systems", IEEE Transactions on Computers, vol. C-20, No. 5, pp. 536-542.

Affiliated with

Also associated with

Rating

Dual-rail processor with error checking at single rail interface does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dual-rail processor with error checking at single rail interface, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual-rail processor with error checking at single rail interface will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-53981