Dual putaway/bypass busses for multiple arithmetic units

Details Dual putaway/bypass busses for multiple arithmetic units Dual putaway/bypass busses for multiple arithmetic units

1984-08-13

1988-08-23

Harkcom, Gary V.

Boots, shoes, and leggings

G06F 738

Patent

active

047665645

ABSTRACT:
A data processing system includes multiple floating point arithmetic units, for example, an adder and a multiplier. Two putaway busses and two bypass busses are connected to a register file and waiting stages, associated with the arithmetic units, respectively. A special source register is included for keeping track of the source of any result on the busses so that the registers may be connected to the appropriate bus on which the result is to appear in accordance with a busy or mark bit set in each register in the file and in the waiting stage. This allows multiple data items to exit the pipes during any cycle. Therefore, two or more results are produced each cycle.

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