Patent
1997-05-09
1999-03-30
An, Meng-Ai T.
395281, G06F 1340
Patent
active
058899707
ABSTRACT:
A core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port ("AGP") bus and host and memory buses, as a bridge between an additional peripheral component interconnect ("PCI") bus and the host and memory buses, or as a bridge between a primary PCI bus and an additional PCI bus. A common bus having provisions for the PCI and AGP interface signals is connected to the core logic chip set and either an AGP or PCI device(s). The core logic chip set also has an AGP/PCI arbiter having additional Request ("REQ") and Grant ("GNT") signal lines so that more than one PCI device may be utilized on the additional PCI bus. Selection of the type of bus bridge (AGP or PCI) in the core logic chip set may be made by a hardware signal input, software during computer system configuration or power on self test ("POST"). Software configuration may also be determined upon detection of either an AGP or PCI device connected to the common bus.
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Horan Ronald Timothy
Olarig Sompong Paul
An Meng-Ai T.
Compaq Computer Corp.
Katz Paul N.
Kim Harold J.
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