Dual processor image compressor/expander

Details Dual processor image compressor/expander Dual processor image compressor/expander

1989-12-01

1991-03-12

Coles, Sr., Edward L.

Facsimile and static presentation processing

Facsimile

Auxiliary signal

358426, 358444, 3582614, H04N 1415

Patent

active

049997157

ABSTRACT:
An image compression and expansion processor includes a dual port memory configured with image and compressed data processing blocks, a host processor for managing movement of predefined blocks of data between an external frame store memory and the dual port memory, and a digital signal processor for compressing or expanding the data stored in the dual port memory. Because minimum redundancy encoding and decoding is employed to reduce the data stream according to the complexity of the image, data streams of undefined length (relative to the predefined blocks of data) are periodically resident in the compressed processing block. By maintaining bit length definition of the data in the compressed block (relative to the predefined blocks), the host processor is able to move defined lengths of compressed data from the dual port memory while the digital signal processor is concurrently processing the predefined blocks of image data.

REFERENCES:
patent: 4394774 (1983-07-01), Widergren et al.
patent: 4772956 (1988-09-01), Roche et al.
patent: 4774587 (1988-09-01), Schmitt
patent: 4947342 (1990-08-01), Katsura et al.

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