Dual port ram

Details Dual port ram Dual port ram

1996-07-23

1998-09-22

Zarabian, A.

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

36518905, 36523005, G11C 800

Patent

active

058124861

ABSTRACT:
A structure for the data processing device, including a memory cell array part having a plurality of memory cells for storing data, first and second address terminals for receiving address signals, a first controller for receiving a first read signal and generating a first read control signal, a second controller for receiving a second read signal and generating a second read control signal, a first latch circuit for holding data provided by a memory cell corresponding to an address signal provided at the first address terminal in response to the first read control signal, and a second latch circuit for holding data provided by a memory cell corresponding to the address signal provided at the second address terminal in response to the second read control signal.

REFERENCES:
patent: 5323355 (1994-06-01), Kato
patent: 5375089 (1994-12-01), Lo
patent: 5572477 (1996-11-01), Juns

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