Dual-port memory with inhibited random access during transfer cy

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395164, 3642448, 364DIG1, 3642441, G11C 1900, G11C 700

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active

052106390

ABSTRACT:
In a video computer system having a dual-port bit-mapped RAM unit incorporating a shift register, provision is made for coupling data between column lines and the shift register, and for simultaneously preventing any column line from being coupled with the random data output terminal of the RAM unit. Accordingly, this prevents two or more different data bits from appearing simultaneously from the RAM unit and causing confusion as to which is the valid signal and which is a spurious signal.

REFERENCES:
patent: 3869603 (1975-03-01), Auspurg et al.
patent: 4023142 (1977-05-01), Woessner
patent: 4417304 (1983-11-01), Dinwiddie
patent: 4541075 (1985-09-01), Dill
IBM Technical Disclosure Bulletin, vol. 23, No. 8, Jan. 1981, "All Points-Addressable Raster Scan Graphics for Cathode Raytube with Dual-Ported Bit Map", pp. 3553-3555.
Analysis and Design of Digital Integrated Circuits, by Hodges, et al., Copyright to 1983, pp. 359-397.

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