Dual-port memory having pipelined serial output

Details Dual-port memory having pipelined serial output Dual-port memory having pipelined serial output

1989-04-07

1990-01-02

Moffitt, James W.

Static information storage and retrieval

Addressing

Plural blocks or banks

36523005, 365236, G11C 800

Patent

active

048917958

ABSTRACT:
A dual-port memory which features a pipelined serial port is disclosed. The serial side of the dual-port memory contains a ripple counter which is broken between predetermined stages. The contents of the stages above the break are decoded to select a group of bits of the serial register for output, and the contents latched in a latch. In serial output, the contents of the stages below the break are decoded, so that responsive to the stages below the break reaching a certain value, the stages above the break are incremented and the incremented value decoded. Pass transistors between the register and the latch are turned off during such time as the incremented value is being decoded, so that the new value will not disturb the output. The latched output is selectively presented by a multiplexer which selects the latch bits responsive to the value of the stages below the break. Upon the value of the stages reaching its minimum value (i.e., the first bit of the next group), the pass transistors are enabled so that the contents corresponding to the incremented contents of the stages above the break are next presented at the output. Logic is provided so that during serial input the stages are not broken, to prevent the early incrementing of the counter prior to storage of the input data. Logic is also provided so that, initially after the counter is loaded with a new value, the first bits are output without being disturbed by an early incrementing of the counter stages above the break.

REFERENCES:
patent: 4633441 (1986-12-01), Ishimoto
patent: 4817058 (1989-03-01), Pinkham

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