Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2000-08-31
2001-07-10
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S189040, C365S189050
Reexamination Certificate
active
06259650
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the synchronization of address pointers across multiple clock domains, and in particular to a dual port First-In-First-Out (FIFO) memory which synchronizes a write and a read pointer across clock domains.
BACKGROUND OF THE INVENTION
A FIFO memory is a well-known type of memory which has numerous applications in electronic circuits and systems. A FIFO memory stores elements on a stack so that the oldest elements are removed first. In many applications, one process may add elements to the stack. This process is termed the write process. Another process may remove elements from the stack. This process is termed the read process. The write process must maintain an address pointer so that it can add elements to the stack. Similarly, the read process must maintain an address pointer so that it can remove elements from the stack.
In many applications, the FIFO memory is implemented using a dual port RAM (DPRAM). One port is used by the write process and the other port is used by the read process. The write process begins by storing an element at the lowest available memory location. The write process then adds elements at sequential memory locations by incrementing a write pointer. When the write process reaches the highest available memory location, the write pointer is incremented to return to the lowest available memory location. Accordingly, the FIFO memory operates in a circular fashion.
The read process begins by removing the element from the lowest available memory location. The read process then continues to remove elements at sequential memory locations by incrementing the read pointer. When the read pointer catches up to the write pointer the memory is empty and the read process stops removing elements from the FIFO stack. When the write pointer catches up to the read pointer, the memory is full and the write process stops adding elements.
In many applications, the write process and the read process operate in different clock domains. Accordingly, circuitry must be provided to generate the write pointer in one clock domain and to generate the read pointer in the other clock domain. In addition, the circuitry must synchronize the write and read pointers across clock domains so that the write process adds elements to empty memory locations and so that the read process removes elements from valid memory locations. This synchronization can introduce significant delays between the read and write processes. In addition, the synchronization often involves complicated custom circuitry, generally not available from CMOS standard cell libraries. Development of such custom circuitry would introduce additional cost and time.
SUMMARY OF THE INVENTION
According to one aspect of the invention, a FIFO includes a memory, a write port, a read port, and a first and a second synchronization circuit. The memory is configured to store a FIFO stack. The write port is configured to add elements to the FIFO stack based upon a write address pointer. The write port operates in a first clock domain. The read port is configured to read elements from the FIFO stack based upon a read address pointer. The read port operates in a second clock domain, different from the first clock domain. The first synchronization circuit is operationally coupled with the write port and is configured to receive the write address pointer and synchronize the write address pointer to the second clock domain. The second synchronization circuit is operationally coupled with the read port and is configured to receive the read address pointer and synchronize the read address pointer to the first clock domain.
According to another aspect of the invention, a synchronizer circuit, suitable for coordinating address pointers across clock domains, includes a first and second timing flip-flop and an inversion circuit. The first timing flip-flop is configured to generate first timing signals. The first timing flip-flop operates in a first clock domain. The inversion circuit is operationally coupled with the first timing flip-flop and is configured to generate inverted timing signals based upon the first timing signals. The second timing flip-flop is operationally coupled with the inverter and is configured to generate second timing signals based upon the inverted timing signals. The second timing flip-flop operates in a second clock domain, different from the first clock domain.
REFERENCES:
patent: 4891788 (1990-01-01), Kreifels
patent: 5294983 (1994-03-01), Ersoz et al.
patent: 5426756 (1995-06-01), Shyi et al.
patent: 5544104 (1996-08-01), Chauvel
patent: 5555524 (1996-09-01), Castellano
patent: 5630096 (1997-05-01), Zuravleff et al.
patent: 5644604 (1997-07-01), Larson
patent: 5748551 (1998-05-01), Ryan et al.
patent: 5784582 (1998-07-01), Hughes
patent: 5787457 (1998-07-01), Miller et al.
patent: 5811995 (1998-09-01), Roy et al.
patent: 5835752 (1998-11-01), Chiang et al.
patent: 5852608 (1998-12-01), Csoppenszky et al.
patent: 5857005 (1999-01-01), Buckenmaier
patent: 5884100 (1999-03-01), Normoyle et al.
patent: 5905766 (1999-05-01), Nguyen
patent: 5931926 (1999-08-01), Yeung et al.
patent: 6000037 (1999-12-01), Herbert
patent: 6006340 (1999-12-01), O'Connell
Girard & Equitz LLP
Le Vu A.
National Semiconductor Corporation
Nguyen Hien
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