Dual port memory

Details Dual port memory Dual port memory

1991-04-09

1994-01-04

Bowler, Alyssa H.

Static information storage and retrieval

Magnetic bubbles

Guide structure

36523005, 36518904, 364DIG1, G06F 1200, G06F 1300

Patent

active

052768422

ABSTRACT:
A dual port memory 50 comprises two decoders 9a, 9b, and two sense amplifiers 14a, 14b, associated with a memory cell array 100. The dual port memory 50 can be accessed by a CPU 6 of the A system side and a CPU 7 of the B system side simultaneously. The occurrence of contention between the accesses of CPUs 6 and 7 with respect to the same memory cell is detected by an access contention detecting circuit 51. In response to contention detection, a control signal generating circuit 52 generates various control signals. The A port side and B port side of the dual port memory 50 each is provided with write data latches 53a, 53b, read data latches 54a, 54b, switches 55a-57b, select switches 58a, 58b, and tri-state buffers 59a and 59b, respectively, to perform arbitration all the time of access contention, in accordance with the control signal from control signal generating circuit 52.

REFERENCES:
patent: 4860263 (1989-08-01), Mattausch
patent: 4937781 (1990-06-01), Lee et al.
patent: 5146572 (1992-09-01), Bailey et al.
patent: 5157775 (1992-10-01), Sanger
"Mikroprozessor-Kommunikation mit Mikrocontrollern ohne Wait-States", by David Bell et al. No. 3, vol. 3, Feb. 1987, pp. 44-46, Elektronik Applikation.

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