Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1982-10-01
1986-10-28
Heyman, John S.
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
307470, 307514, 328109, 364200, H03K 1728, H03K 526
Patent
active
046201181
ABSTRACT:
Two microprocessors, which may be operating asynchronously, share a random access memory (RAM) array; that is, at any one moment of time, either microprocessor can seek access to the RAM but only one of them can actually gain access at a time. Priority of access to the RAM is controlled by a dual port contention-resolving access circuit which enables such access alternately to the two microprocessors when both are seeking (overlapping) access, subject to the stipulation when neither microprocessor is accessing the RAM that the very next access will be allocated by the circuit on a first-come first-served basis, and will be allocated to a preselected one of the microprocessors if both microprocessors will commence to seek access precisely at the same time.
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J. Nadir et al, "Dynamic-RAM-Controller Orchestrates Memory Systems," Electronics, Sep. 8, 1982, pp. 128-133.
S. Libes, Fundamentals and Applications of Digital Logic Circuits, 1975, pp. 102-105.
AT&T Bell Laboratories
Caplan David I.
Heyman John S.
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