Dual polarity floating gate MOS analog memory device

Details Dual polarity floating gate MOS analog memory device Dual polarity floating gate MOS analog memory device

1989-08-28

1991-06-25

Wojciechowicz, Edward J.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 234, 357 42, 365182, H01L 2978, G11C 1134

Patent

active

050271717

ABSTRACT:
A dual-polarity nonvolatile MOS analog memory cell is disclosed that comprises two pairs of complementary metal oxide field effect transistors. Each pair includes a p-channel and an n-channel transistor. The gates of each transistor are all operably coupled in common to form a common floating gate. The sources of the transistors of the first transistor pair are operably coupled to a common ground. The sources of the second pair of transistors are operably coupled together to form an output junction. Positive voltage applied to the drain of the n-channel transistor of the first transistor pair causes a positive analog value to be stored in memory when there previously was no value stored in memory, or increases a value previously stored in memory. Negative voltage applied to the drain of the p-channel transistor of the first transistor pair causes a negative analog value to be stored in memory when there previously was no value stored in memory, or decreases a value previously stored in memory.

REFERENCES:
Shimabukuro et al.--1989 IEEE International Symposium on Circuits and Syss, Proceedings, vol. 2, IEEE, May 8-11, 1989.
Shoemaker et al.--"Artificial Neural Network Implementation with Floating Gate MOS Devices"--Hardware Implementation of Neuron Nets and Synapses, Workshop sponsored by NSF and ONR, Jan. 14-15, 1988.

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