Dual pipelined interconnect

Details Dual pipelined interconnect Dual pipelined interconnect

1997-05-01

1999-05-25

Sheikh, Ayaz R.

395310, 395872, G06F 1338

Patent

active

059076917

ABSTRACT:
An interface circuit receives both priority and non-priority information non-concurrently on a shared input bus during a first clock cycle and transmits the information received during the first clock cycle non-concurrently to a shared output bus during a second clock cycle following the first clock cycle. The received information includes status data identifying it as being either priority or non-priority information. All received information is provided to an external circuit via either a priority information path or a non-priority information path, depending on whether the status data included with the information identifies it as being priority or non-priority information. When the interface circuit is unable to transmit information, received information is backed up into either a priority or a non-priority information path, depending on whether the status data included with the information identifies it as being priority or non-priority information. When information is provided from the external circuit to the output of the interface circuit, it may pass though either a priority or a non-priority information path, depending on whether the information identified as being priority or non-priority information.

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