Dual pipeline superscalar reduced instruction set computer syste

Details Dual pipeline superscalar reduced instruction set computer syste Dual pipeline superscalar reduced instruction set computer syste

1997-01-16

1998-04-21

Harrell, Robert B.

G06F 930

Patent

active

057427801

ABSTRACT:
A microprocessor core operating on instructions in a dual six-stage pipeline. Instructions are fetched and decoded by an instruction scheduling unit which includes a queuing stage for facilitating conditional branch operations. Instructions can be executed in five execution units including a load/store/add unit, an ALU unit, a shift/multiply unit, a branch unit, and a coprocessor which interfaces with the microprocessor core. Exceptions are handled by the coprocessor which includes a plurality of registers and a multiple entry translation lookaside buffer and an exception program counter. When an exception is detected the coprocessor loads the exception program counter with a restart address where execution can resume after the exception is serviced, the plurality of registers being used during the exception processing. One of the registers is a circulate mask register which is used by the coprocessor in executing an Add with Circular Mask instruction in which an immediate field of the instruction is sign-extended and added to the contents of a general register, the result being masked with the extended value in the circular mask register.

REFERENCES:
patent: 5193206 (1993-03-01), Mills
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patent: 5440749 (1995-08-01), Moore et al.
patent: 5471598 (1995-11-01), Quattromani et al.
patent: 5530890 (1996-06-01), Moore et al.
patent: 5537581 (1996-07-01), Conary et al.

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