Dual phased-locked loop structure having configurable...

Details Dual phased-locked loop structure having configurable... Dual phased-locked loop structure having configurable...

2005-11-29

2005-11-29

Nguyen, Minh (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S156000

Reexamination Certificate

active

06970030

ABSTRACT:
A PLL function may be implemented as a dual-loop structure having a first PLL circuit which generates an intermediate signal from the reference signal, and a second PLL circuit which generates an output signal from the intermediate signal. The intermediate signal frequency is preferably chosen at a value in which potential interference signals do not have much energy. The first loop preferably has low bandwidth to provide good input jitter attenuation, while second loop preferably has higher bandwidth to reduce phase noise of the output signal. The circuit preferably provides for a choice of several different intermediate frequencies to allow use where different intermediate frequencies may exist in each system. Moreover, in a system having two such dual-loop PLL circuits, each can be configured with a different intermediate frequency, so that interference from one to the other is reduced.

REFERENCES:
patent: 6067335 (2000-05-01), Yamanoi et al.
patent: 6114987 (2000-09-01), Bjornholt
patent: 6163684 (2000-12-01), Birleson
patent: 6188258 (2001-02-01), Nakatani
patent: 6218876 (2001-04-01), Sung et al.
patent: 6703876 (2004-03-01), Fujiwara et al.

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