Dual phase-locked-loop having forced mid range fine control zero

Details Dual phase-locked-loop having forced mid range fine control zero Dual phase-locked-loop having forced mid range fine control zero

1992-04-24

1994-11-08

Chin, Stephen

Pulse or digital communications

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331 1A, 331 25, 331 14, H03D 324

Patent

active

053634195

ABSTRACT:
Method and apparatus for controlling a PLL so that handover between fine and coarse loops take place at 2.5% of the nominal VCO frequency and where the coarse and fine loops error are combined in a summer circuit which employs a series circuit having a P-channel and N-channel FET with common drains and where the drains connected to the summer output node.

REFERENCES:
patent: 4272729 (1981-06-01), Riley, Jr.
patent: 4965533 (1990-10-01), Gilmore
patent: 5015970 (1991-05-01), Williams et al.

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