Dual phase-locked loop clock synthesizer

Details Dual phase-locked loop clock synthesizer Dual phase-locked loop clock synthesizer

1996-08-15

1998-03-31

Mis, David

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural oscillators controlled

331 1A, 331 17, 331 25, 331 34, 327148, 327150, 375374, 375376, H03L 707, H03L 7089

Patent

active

057343012

ABSTRACT:
A dual phase-locked loop (PLL) clock synthesizer is disclosed for generating clock signal in synchronization with the data input signal received over a network environment. The dual PLL clock synthesizer is suitable for processing data streams of any bit sequence without data error caused by interference due to clock signal jittering phenomena. The dual PLL clock synthesizer is particularly suitable for application to high-speed Ethernet network environment such as for decoding to obtain the original data conveyed over the network through selected encoding scheme.

REFERENCES:
patent: 5546052 (1996-08-01), Austin et al.
"A 200 MH.sub.z CMOS Phase-Locked Loop with Dual Phase Detectors", IEEE Journal of Solid-State Circuits, vol. 24, No. 6, Dec. 1989, Ware K.M. et al, pp. 1560-1568.

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