Dual-phase delay-locked loop circuit and method

Details Dual-phase delay-locked loop circuit and method Dual-phase delay-locked loop circuit and method

2005-06-14

2005-06-14

Nguyen, Linh My (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S161000

Reexamination Certificate

active

06906566

ABSTRACT:
A delay-locked loop includes a clock multiplier that generates a multiplied clock signal responsive to an input clock signal. The multiplied clock signal has a frequency that is a multiple of a frequency of the input clock signal. A variable delay circuit generates a delayed clock signal responsive to the multiplied clock signal, the delayed clock signal having a delay relative to the multiplied clock signal. The variable delay circuit controls the value of the delay responsive to a delay control signal. A comparison circuit generates the delay control signal in response to the relative phases of the delayed clock signal and the multiplied clock signal. In another embodiment, the delay-locked loop omits the clock multiplier and instead includes a comparison circuit that generates the delay control signal in response to the relative phases of both the rising- and falling-edge transitions of the delayed and input clock signals.

REFERENCES:
patent: 4965810 (1990-10-01), Peischl et al.
patent: 5036528 (1991-07-01), Costantino et al.
patent: 5077686 (1991-12-01), Rubinstein
patent: 5233316 (1993-08-01), Yamada et al.
patent: 5525939 (1996-06-01), Yamauchi et al.
patent: 5574508 (1996-11-01), Diamant
patent: 5614845 (1997-03-01), Masleid
patent: 5675273 (1997-10-01), Masleid
patent: 5757218 (1998-05-01), Blum
patent: 5910740 (1999-06-01), Underwood
patent: 5923715 (1999-07-01), Ono
patent: 5946244 (1999-08-01), Manning
patent: 5955905 (1999-09-01), Idei et al.
patent: 5956289 (1999-09-01), Norman et al.
patent: 5969552 (1999-10-01), Lee et al.
patent: 6067648 (2000-05-01), Hunter et al.
patent: 6069508 (2000-05-01), Takai
patent: 6087868 (2000-07-01), Millar
patent: 6107891 (2000-08-01), Coy
patent: 6150856 (2000-11-01), Morzano
patent: 6150892 (2000-11-01), Lee et al.
patent: 6160755 (2000-12-01), Norman et al.
patent: 6194932 (2001-02-01), Takemae et al.
patent: 6239641 (2001-05-01), Lee
patent: 6240042 (2001-05-01), Li
patent: 6304117 (2001-10-01), Yamazaki et al.
patent: 6310822 (2001-10-01), Shen
patent: 6323705 (2001-11-01), Shieh et al.
patent: 6330197 (2001-12-01), Currin et al.
patent: 6340904 (2002-01-01), Manning
patent: 6373307 (2002-04-01), Takai
patent: 6378079 (2002-04-01), Mullarkey
patent: 6380811 (2002-04-01), Zarubinsky et al.
patent: 6404248 (2002-06-01), Yoneda
patent: 6417715 (2002-07-01), Hamamoto et al.
patent: 6426900 (2002-07-01), Maruyama et al.
patent: 6445231 (2002-09-01), Baker et al.
patent: 6476653 (2002-11-01), Matsuzaki
patent: 6480047 (2002-11-01), Abdel-Maguid et al.
patent: 6484268 (2002-11-01), Tamura et al.
patent: 6490207 (2002-12-01), Manning
patent: 6509776 (2003-01-01), Kobayashi et al.
patent: 6556489 (2003-04-01), Gomm et al.
patent: 6605969 (2003-08-01), Mikhalev et al.
patent: 6625765 (2003-09-01), Krishnan
patent: 6693472 (2004-02-01), Mikhalev et al.
patent: RE38482 (2004-03-01), Leung et al.
patent: 6759911 (2004-07-01), Gomm et al.
patent: 2002/0167346 (2002-11-01), Yoon et al.
patent: 2002/0176315 (2002-11-01), Graaff
patent: 2002/0180499 (2002-12-01), Kim et al.
Chae, Jeong-Seok et al., “Wide Range Single-Way-Pumping Synchronous Mirror Delay”, IEEE Electronics Letter Online No. 20000711, Feb. 11, 2000, pp. 939-940.
Jang, Seong-Jin et al., A Compact Ring Delay Line for High Speed Synchronous DRAM, IEEE Symposium on VLSI Circuits Digest of Technical Papers, 1998, pp. 60-61.
Kuge, Shigehiro et al., “A 0.18 μm 256Mb DDR-SDRAM with Low-Cost Post-Mold-Tuning Method for DLL Replica”, IEEE International Solid-State Circuits Conference, Feb. 2000, pp. 402-403.
Saeki, Takanori et al., “A 2.5ns Clock Access 250MHz 256Mb SDRAM with a Synchronous Mirror Delay”, IEEE International Solid-State Circuits Conference, Feb. 1996, pp. 374-375.
Takai, Yasuhiro et al., A 250Mb/s/pin 1Gb Double Data Rate SDRAM with a Bi-Directional Delay and an Inter-Bank Shared Redundancy Scheme, 1999.
Kuge, Shigehiro et al., “A 0.18-μm 256-Mb DDR-SDRAM with Low-Cost Post-Mold Tuning Method for DLL Replica”, IEEE Journal of Solid-State Circuits, vol. 35, No. 11, Nov. 2000, pp. 1680-1689.

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