Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform
Reexamination Certificate
1999-05-07
2001-07-03
Ton, My-Trang Nu (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Having specific delay in producing output waveform
C327S285000
Reexamination Certificate
active
06255878
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention pertains to a dual path asynchronous delay circuit for introducing a delay into a system.
In telecommunications systems, bus interface systems and the like, it is sometimes desirable to delay certain signals to permit other portions of the system to respond to signal changes. For example, a bus expander circuit may delay signals on a primary bus to permit adequate turnaround time for signals on a secondary bus.
Analog delay cells have been developed for use in electronic circuitry to delay signals. Either the current or voltage available to a device can be varied, or the capacitive loading can be varied, to introduce a variable delay. A variable delay element can thus be built using inverters or other circuit devices.
A problem concerning the production of analog delay cells is that currents for p-channel and n-channel devices cannot be exactly matched. The inherent variations in processing, and differences in temperature and voltage, may result in devices that exhibit asymmetric drive. The asymmetric drive increases or decreases the pulse width of the signal as the signal pulse travels through a chain of delay cells, resulting in distortion or loss of the signal.
Another problem is that the delay of each cell in a chain of delay cells defines the minimum pulse width of a signal required to ensure that the signal will propagate through the entire chain. If a signal pulse width is too narrow, then as the signal propagates through consecutive stages of the delay chain at some point it will not attain a voltage sufficient to produce an output. Thus, it would be beneficial to develop a delay circuit that can propagate and delay a small pulse having a pulse width that is less than or equal to the delay provided by each delay cell.
SUMMARY OF THE INVENTION
The invention pertains to a dual delay chain precision delay circuit having a first flip-flop configured to be triggered by a rising edge of an input pulse signal and a second flip-flop configured to be triggered by the falling edge of the input pulse signal. A first delay chain of delay cells has a first delay cell connected to a first output line, and a second delay chain of delay cells has a first delay cell connected to a second output line. The delay cells of the first and second delay chains produce first and second delay outputs. A delay latch is connected to the first and second delay chains and has a delay output. The delay latch is set by the first delay output signal and reset by the second delay output signal. As a result, the pulse width of the delay circuit output is equal to the pulse width of the input pulse signal.
Implementations of the invention may contain one or more of the following features. The delay cells of the first and second delay chains may be interleaved. The circuit may include a first feedback loop connected to the output of a preselected delay cell of the first delay chain and connected to a reset input of the first flip-flop. Similarly, the circuit may include a second feedback loop connected to the output of a preselected delay cell of the second delay chain and connected to a reset input of the second flip-flop. The first and second delay chains may comprise matched delay cells. A first exclusive-OR circuit having a first input may be connected to the first delay output, and a second input of the exclusive-OR circuit may be connected to the output of a delay cell that is positioned before the end of the first delay chain. In addition, a second exclusive-OR circuit may have a first input connected to the second delay output and a second input may be connected to the output of a delay cell that is positioned before the end of the second delay chain, wherein the first exclusive-OR circuit generates a signal to set the delay latch and the second exclusive-OR circuit generates a signal to reset the delay latch.
In another implementation, a method for introducing a delay for a pulse signal includes introducing a rising edge of the pulse signal to a first delay chain of a plurality of delay cells and introducing a falling edge of the pulse signal to a second delay chain of a plurality of delay cells. The rising and falling edges of the pulse signal are then propagated through the delay chains. A latch is set with the output of the first delay chain and reset with the output of the second delay chain. The result is that the pulse width of the input signal is preserved.
Implementations of the technique may include one or more of the following features. The rising edge of the input signal may clock a first flip-flop, and the falling edge of the input signal may clock a second flip-flop. A first exclusive-OR circuit may generate a signal to reset the latch.
Another aspect of the invention concerns a delay circuit for generating a delayed assertion signal. The delay circuit includes a clock toggle circuit element connected to a signal input line. The input of a delay chain of a plurality of delay cells connected in series is connected to the output of the toggle circuit element. The complement of a reset signal is connected to a first input of an AND circuit and the output of a delay cell within the delay chain is connected to a second input of the AND circuit. The output of the AND circuit is connected to a low active input of the toggle circuit element. An OR circuit has a first input connected to the signal line and a second input connected to a reset signal. A latch circuit has a first input connected to the output of the OR circuit and a second input connected to the output of the delay chain, and asserts the output signal in response to assertion of the signal input line. The latch circuit is clocked by the output of the delay chain to de-assert the output signal to produce a delayed de-assertion of the output signal. The output signal produced by the delay circuit is insensitive to the pulse width of the input signal.
A technique for implementing the delay circuit to generate a delayed de-assertion signal that is independent of the pulse width of an input signal includes feeding the input signal to a latch circuit to assert an output signal. The input signal is also provided to a toggle circuit element, and the output of the toggle circuit element propagates through a delay chain of a plurality of delay cells. The output of a delay cell positioned within the delay chain is fed-back to reset the toggle circuit element. Lastly, a generated delay chain output signal clocks the latch circuit to de-assert the delay circuit output signal.
An implementation of the technique may include the following feature. The output of the particular delay cell in the delay chain for feedback may be chosen based on the point within the delay chain at which an input pulse will survive propagation through the remainder of the delay chain.
Advantages of the invention include providing a precision delay circuit architecture in a small area of silicon that can introduce a delay of a predetermined interval. Thus, a large delay can be implemented in a small area, in contrast to using numerous delay cells connected together which take up valuable real estate on a silicon chip and which may cause other signal delay problems.
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Gauvin Coralyn S.
Herbert Brian K.
Petty William K.
Fish & Richardson P.C.
LSI Logic Corporation
Nu Ton My-Trang
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