Dual operating speed switchover arrangement for CPU

Details Dual operating speed switchover arrangement for CPU Dual operating speed switchover arrangement for CPU

1985-12-12

1989-04-11

Shaw, Gareth D.

Boots, shoes, and leggings

307269, G06F 100, G04G 700

Patent

active

048212296

ABSTRACT:
A user selectable switch arrangement in combination with logic circuitry allows the timing of a central processor unit (CPU) to be switched between two clock frequencies. Operation at a higher frequency permits the CPU to perform an increased number of tasks per unit time and thus increases data throughput, while a lower operating frequency provides enhanced CPU hardware and software interfacing compatibility.

REFERENCES:
patent: 3623017 (1971-11-01), Lowell et al.
patent: 4229699 (1980-10-01), Frissell
patent: 4435827 (1984-03-01), Kuze
patent: 4677433 (1987-06-01), Catlin et al.
patent: 4727491 (1988-02-01), Culley
Intel "Microprocessor and Peripheral Handbook", 1983, pp. 3-234-3-241.

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