Dual-modulus prescaler

Details Dual-modulus prescaler Dual-modulus prescaler

2001-06-12

2002-05-07

Wambach, Margaret R. (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Pulse multiplication or division

C377S048000

Reexamination Certificate

active

06385276

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to circuitry for counting or dividing. More particularly, the present invention relates to frequency prescaler circuits. Still more particularly, the present invention relates to dual modulus prescaler circuits for use in frequency synthesizers.
BACKGROUND OF THE INVENTION
Prescaler circuits for use in high-speed dividers, frequency synthesizers and the like are well known in the art. A dual modulus prescaler is a divider whose division ratio or modulus can be switched from one value to another by a control signal. Commonly known implementations of prescalers utilize a counter circuit consisting of series-coupled flip-flop circuits that are used to obtain an output whose frequency is a fraction of that of a clock signal. Thus, a prescaler can divide by a first factor when a control signal has a first state or by a second factor when the control signal has a second state. Aspects of prescaler circuits and component dual modulus dividers used in a variety of RF contexts are described generally in B. Razavi,
RF Microelectronics
, Prentice-Hall PTR, 1998, especially pp. 269-297.
Many electronic devices, including mobile radiotelephones operating in the 800-900 MHz and higher frequency bands require prescalers operating at correspondingly high frequencies under a variety of conditions. Further, many such applications of prescaler circuits place low power dissipation requirements for to enhance portability and extend period of use between battery recharges. In addition, prescalers for use in many portable devices advantageously operate at low supply voltage levels.
FIG. 1
shows a typical prior art prescaler circuit
100
comprising three sub-circuits: a synchronous dual-modulus divider (illustratively a divide by 4/5 divider)
105
; a fixed-modulus divider (illustratively divide by 8)
110
; and decode logic
115
.
As suggested by its name, synchronous dual-modulus divider
105
will, depending on the state of divider control signal divc on path
135
, divide an input frequency clock signal fin (applied on path
120
to each of three D-type flip-flops
145
,
150
and
157
) by either 4 or 5. Each of flip-flops
145
,
150
and
157
has a Q and a/Q (Q-bar) output, and feedback paths from the Q outputs of flip-flops
150
and
157
to the D input to flip-flop
145
(input D
1
).
Fixed modulus divider
110
in
FIG. 1
receives divided clock pulses fb from dual-modulus divider
105
over path
130
to flip-flop
180
-
1
and counts them in standard fashion using flip-flops
180
-i, i=1, 2, 3. In particular, transitions of flip-flop
180
-
1
are triggered by rising edges of divided clock pulses on fb. Output fout appearing on path
125
is the desired divided output frequency signal. In selectively supplying binary state signals for divc, decode logic
115
, including AND gates
160
and
165
, receives inputs from flip-flops
180
-i in fixed modulus divider
110
and a modulus control signal mc on lead
170
.
In one application of the circuit of
FIG. 1
, operation as either a divide-by-32 or divide-by-33 circuit is achieved. Divide-by-32 operation is obtained if the dual-modulus divider
105
operates in divide-by-4 mode for eight cycles, accounting for 32 cycles of the input clock signal fin on path
120
. These eight cycles of dual-modulus divider
105
comprise one full cycle of the fixed modulus divider
110
and, therefore, of prescaler
100
. Divide-by-33 operation is obtained if dual-modulus divider
105
operates in divide-by-5 mode for one cycle (five cycles of input clock fin), and in divide-by-4 mode for seven cycles (28 cycles of fin), for a total of 33 cycles of fin. The eight cycles of dual-modulus divider
110
again comprise one full cycle of the fixed-modulus divider
100
, and therefore of prescaler
100
.
The divc signal on path
135
determines the mode of operation of the dual-modulus divider
105
. If divc is in a first state, then dual-modulus divider
105
operates in a divide-by-4 mode, and if divc is in a second state, then dual-modulus divider
105
operates in a divide-by-5 mode. For proper operation, divc must be held in one of its two states for approximately one cycle of dual-modulus divider
105
. In typical applications of prescaler
100
selection of divide-by-32 or divide-by-33 mode is performed by a circuit external to prescaler
100
. This external circuit may be a programmable divider that receives output signal fout as its clock and generates modulus control signal mc on path
170
. The mc signal will appear in one or the other of its states for the duration of one or more periods of fout. Decode logic
115
uses the mc signal and decodes the state of fixed modulus divider
110
to generate divc in a state corresponding to the state of mc for the required duration (approximately one cycle of dual-modulus divider
105
).
FIGS. 2A and 2B
are state transition diagrams for the divide-by-4 and divide-by-5modes of operation of divide circuit
105
of FIG.
1
. In particular, each of these state transition diagrams show eight states represented by a three-bit sequence (Q
1
Q
2
Q
3
) associated with flip flops
145
,
150
and
157
, with the most significant bit (MSB) corresponding to the Q output of flip-flop
145
(Q
1
), the next bit corresponding to the Q output of flip-flop
150
(Q
2
), and the least significant bit (LSB) corresponding to the Q output of flip-flop
157
(Q
3
). The state machine reflected by
FIGS. 2A and 2B
is clocked by input clock signal fin on path
120
to synchronous divider
105
.
Input control to the state machine is provided by divider control signal, divc, on path
135
, with state machine transitions from one state to another during each clock period of the input signal occurring in response to the one-bit divc signal. Transitions are indicated in the
FIGS. 2A and 2B
by directional arrows labeled with divc values x, 0, or 1, where divc=x indicates “don't care,” divc=0 indicates divide-by-4 mode, and divc=1 indicates a divide-by-5 mode. Thus, for example, if divc=0 and flip-flops
145
,
150
and
157
are in respective states 1,0,0 (Q
1
=1; Q
2
=Q
3
=0), then /Q
2
=1, the output of NAND gate
155
is 1, and a 1 is clocked into flip-flop
157
while flip-flops
145
and
150
have
1
's clocked in—thus giving rise to a new state of 111. But, if flip-flops
145
,
150
and
157
exhibit a
110
state (Q
1
=1, Q
2
=1, and Q
3
=0), then the next state will be 111 regardless of whether divc is a 0 or a 1.
In the state transition diagrams of
FIGS. 2A and 2B
, crosshatched states are those from which transitions occur for the respective mode (divide by 4/5). The normal state transition path for the divide-by-4 mode (
FIG. 2A
) is: 111=>011=>001=>101. Similarly, normal sequence of state transitions in the divide-by-5 mode is: 111=>011 =>001=>100=>110. Two of the eight states (010 and 000) are start-up states that are not present in the normal divide by 4 or divide by 5 paths.
FIG. 3
is a timing diagram for operation of prescaler
100
of
FIG. 1
illustrating clocking inputs (fin), states traversed in respective divide-by-5 and divide-by-4 operating modes and the state of each of the fb and divc signals. The waveform for divc in
FIG. 3
shows a maximum allowable delay for the transition from one state to another. In particular, it will be appreciated that, because divc is generated, in part, in response to states of fixed modulus divider
115
, and because states of divider
115
depend, in turn, on fb, a maximum of one input clock cycle can be counted on as the period in which the divc signal will settle after a rising edge occurs in the fb signal.
Since divide-by-4/5 circuits are important elements of prescaler operation, considerable effort has been devoted to insure that reliable high-speed operation is achieved in this sub-circuit. It has also proven desirable to employ relatively lower performan

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