Dual modulus fractional divider

Details Dual modulus fractional divider Dual modulus fractional divider

1988-03-31

1990-01-02

Clark, David L.

Boots, shoes, and leggings

G06F 768

Patent

active

048917745

ABSTRACT:
A dual modulus fractional divider having a dual modulus prescaler coupled to a programmable divider. Latches and a full adder are provided for programming the programming divider with a modulus A, a modulus B, a modulus (A-1) and a modulus (B+1). A rate multiplier controls the adder to provide the desired resolution of the divider.

REFERENCES:
patent: 4241408 (1980-12-01), Gross
P. Higgins et al., "Developing a Slow Clock Rate from a Master Clock which is not an Integral Multiple of the Slow Clock", IBM Technical Disclosure Bulletin, vol. 24, No. 7A, Dec. 1981, pp. 3117-3118.
A. Wallner, "Binary Rate Multiplier Controls AC Power", Contron Engineers, Jan. 1972, pp. 50-51.

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