Dual mode virtual-to-real address translation mechanism

Details Dual mode virtual-to-real address translation mechanism Dual mode virtual-to-real address translation mechanism

1980-01-08

1981-08-18

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 1300

Patent

active

042850401

ABSTRACT:
A mechanism in a computer system translates a program-generated virtual address into a real address of at least a portion, such as a byte, of a segment of the storage of the computer system. The translation mechanism is operable in either of two modes for forming the real storage address. In either mode of operation of the translation mechanism, a first portion of the virtual address is utilized to select a predetermined one of a plurality of segment descriptors, each having a first field portion and a second field portion. The first field portion of the selected segment descriptor indicates whether the structure of the storage segment is comprised of contiguous blocks or noncontiguous subsegments of storage and correspondingly causes operation of the mechanism in the first mode wherein the real address is formulated from the second field portion of the selected segment descriptor and other portions of the virtual address or in the second mode wherein the real address is formulated from another portion of the virtual address and a field portion of a subsegment descriptor selected by the second field portion of the selected segment descriptor.

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G. M. Bull et al., Time-Sharing Systems, McGraw-Hill (UK) Ltd., 1971, pp. 52-60 and 66-86.

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