Dual mode phase-locked loop

Pulse or digital communications – Spread spectrum – Direct sequence

Patent

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Details

Other Related Categories

331 1A, H04L 706

Type

Patent

Status

active

Patent number

053156234

Description

ABSTRACT:
A phase-locked loop is provided for operating in either a steady-state mode or a transient mode. The steady-state mode obtains high rejection of noise disturbances to maintain lock of the phase-locked loop. The transient mode provides a near deadbeat response in order to quickly acquire a new phase-locked loop frequency when a new frequency command is received.

REFERENCES:
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patent: 4940951 (1990-07-01), Sakamoto
patent: 4970474 (1990-11-01), Kennedy et al.
patent: 4987387 (1991-01-01), Kennedy et al.
patent: 5111124 (1992-05-01), Kurosawa
patent: 5113152 (1992-05-01), Norimatsu
patent: 5126693 (1992-06-01), Gulliver et al.
Badger, "Pole-Zero Cancellation Reduces Noise in Phase-Locked Loop Systems", Proc. RF Tech. Expo, Feb. 10, 1988, pp. 157-162.
Horowitz et al., The Art of Electronics, 1980, Cambridge University Press, pp. 428-437.

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