Static information storage and retrieval – Powering – Data preservation
Reexamination Certificate
2008-06-25
2011-10-18
Phung, Anh (Department: 2824)
Static information storage and retrieval
Powering
Data preservation
Reexamination Certificate
active
08040750
ABSTRACT:
A controller of a memory system is configured to reduce power requirements during memory backup transition. When transitioning to backup mode, the memory system controller performs a number of power saving techniques. The controller may change a number of configuration settings in the volatile memory system, such as reducing output driver strength, increasing differential impedance, increasing on-die termination, disabling receiver input circuitry, and disconnecting the termination voltage network. The controller may also assert a hard reset to the storage controller system to significantly reduce the load and allow the voltage regulator to continue to provide power to the memory system for a longer period of time.
REFERENCES:
patent: 4974118 (1990-11-01), Rounds
patent: 5262999 (1993-11-01), Etoh et al.
patent: 5430674 (1995-07-01), Javanifard
patent: 5438549 (1995-08-01), Levy
patent: 5555371 (1996-09-01), Duyanovich et al.
patent: 5644531 (1997-07-01), Kuo et al.
patent: 5661349 (1997-08-01), Luck
patent: 5732238 (1998-03-01), Sarkozy
patent: 5793776 (1998-08-01), Qureshi et al.
patent: 5944837 (1999-08-01), Talreja et al.
patent: 6016472 (2000-01-01), Ali
patent: 6236593 (2001-05-01), Hong et al.
patent: 6282670 (2001-08-01), Rezaul Islam et al.
patent: 6378033 (2002-04-01), Nishikawa
patent: 6496939 (2002-12-01), Portman et al.
patent: 6658435 (2003-12-01), McCall
patent: 6680548 (2004-01-01), Shiue et al.
patent: 6785786 (2004-08-01), Gold et al.
patent: 7143298 (2006-11-01), Wells et al.
patent: 7315951 (2008-01-01), Hanrieder et al.
patent: 7451348 (2008-11-01), Pecone et al.
patent: 2002/0029354 (2002-03-01), Forehand et al.
patent: 2004/0052502 (2004-03-01), Komatsu et al.
patent: 2004/0218434 (2004-11-01), Hwang et al.
patent: 2004/0224192 (2004-11-01), Pearson
patent: 2005/0010838 (2005-01-01), Davies et al.
patent: 2005/0063217 (2005-03-01), Shiraishi et al.
patent: 2005/0283648 (2005-12-01), Ashmore
patent: 2006/0047985 (2006-03-01), Otani
patent: 2006/0108875 (2006-05-01), Grundmann et al.
patent: 2006/0212644 (2006-09-01), Acton et al.
patent: 2006/0248269 (2006-11-01), Shona
patent: 2006/0255746 (2006-11-01), Kumar et al.
patent: 2006/0259756 (2006-11-01), Thompson et al.
patent: 2006/0264188 (2006-11-01), Mars et al.
patent: 2007/0002675 (2007-01-01), Koo
patent: 2007/0033433 (2007-02-01), Pecone et al.
patent: 2007/0133277 (2007-06-01), Kawai et al.
patent: 2007/0180184 (2007-08-01), Sakashita et al.
patent: 2008/0016385 (2008-01-01), Hollingsworth et al.
patent: 2008/0086615 (2008-04-01), Elliott et al.
patent: 2008/0201622 (2008-08-01), Hiew et al.
patent: 2009/0254772 (2009-10-01), Cagno et al.
patent: 2009/0327578 (2009-12-01), Cagno et al.
patent: 2010/0011261 (2010-01-01), Cagno et al.
patent: 2010/0052625 (2010-03-01), Cagno et al.
patent: 2000194607 (2000-07-01), None
patent: 2002312250 (2002-10-01), None
US 7,278,054, 10/2007, Davies et al. (withdrawn)
U.S. Appl. No. 12/146,098, filed Jun. 25, 2008, Cagno, et al.
U.S. Appl. No. 12/204,456, filed Sep. 4, 2008, Cagno, et al.
U.S. Appl. No. 12/169,273, filed Jul. 8, 2008, Cagno, et al.
“Patented Wear Leveling”, BitMicro Networks, http://www.bitmicro.com/products—edisk—features—wearlevel.php, printed Jul. 8, 2008, 2 pages.
U.S. Appl. No. 12/099,373, filed Apr. 8, 2008, Cagno et al.
“Method and Procedure to Minimize Peak Power Load During Backup of Volatile Memory with Flash Memory Devices”, IBM Technical Disclosure, http://www.ip.com/pubview/IPCOM000167428D, Feb. 13, 2008, 6 pages.
Interview Summary mailed Apr. 28, 2011 for U.S. Appl. No. 12/169,273; 3 pages.
Response to Office Action filed Apr. 29, 2011, U.S. Appl. No. 12/169,273, 10 pages.
Response to Office Action filed with the USPTO on Mar. 7, 2011 for U.S. Appl. No. 12/099,373; 14 pages.
U.S. Appl. No. 12/099,373; Mar. 7, 2011, 2 pages.
U.S. Appl. No. 12/146,098; Mar. 7, 2011, 2 pages.
U.S. Appl. No. 12/169,273; Mar. 7, 2011, 2 pages.
U.S. Appl. No. 12/204,456; Mar. 7, 2011, 1 page.
Kim, Jesung et al., “A Space-Efficient Flash Translation Layer for CompactFlash Systems”, IEEE Transactions on Consumer Electronics, May 2002, vol. 48, No. 2, pp. 366-375.
Thomasian, Alexander, “Priority Queueing in Raid5 Disk Arrays with an NVS Cache”, Modeling, analysis, and Simulation of Computer and Telecommunication Systems, 1995. MASCOTS '95., Proceedings of the Third International Workshop on, vol., no., pp. 168-172, Jan. 18-20, 1995 doi: 10.1109/MASCOT.1995.378692.
Varma, Anujan et al., “Destage Algorithms for Disk Arrays with Nonvolatile Caches”, Computers, IEEE Transactions on, vol. 47, No. 2, pp. 228-235, Feb. 1998 doi: 10.1109/12.663770, URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=663770&isnumber=14539.
Response to Office Action filed with the USPTO on May 24, 2011 for U.S. Appl. No. 12/146,098, 15 pages.
“Using Compression to Expedite Hardening Process of a Non-Volatile Memory DIMM System”, IBM Technical Disclosure, http://www.ip.com/pubview/IPCOM000167472D, Feb. 15, 2008, 4 pages.
Notice of Allowability mailed Jun. 13, 2011 for U.S. Appl. No. 12/169,273, 3 pages.
Notice of Allowance mailed Jun. 9, 2011 for U.S. Appl. No. 12/169,273, 9 pages.
Office Action mailed Jun. 22, 2011 for U.S. Appl. No. 12/099,373, 12 pages.
Final Office Action mailed Jul. 28, 2011 for U.S. Appl. No. 12/146,098, 19 pages.
Cagno Brian J.
Elliott John C.
Lucas Gregg S.
Bluestone Randall J.
International Business Machines - Corporation
King Douglas
Phung Anh
Walder, Jr. Stephen J.
LandOfFree
Dual mode memory system for reducing power requirements... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dual mode memory system for reducing power requirements..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual mode memory system for reducing power requirements... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4282988