Dual mode memory read cycle time reduction system which generate

Details Dual mode memory read cycle time reduction system which generate Dual mode memory read cycle time reduction system which generate

1987-12-18

1991-07-16

Williams, Jr., Archie E.

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364270, 3642703, 364271, 3642386, 3642387, 3642715, 3642716, 364239, 3642391, 3642445, 364244, 364934, 3649342, 3649344, 3649332, 3649337, 3649394, 364968, 3649657, 364965, 364950, 3649503, 3649504, G06F 1300, G06F 104, G06F 506

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active

050330012

ABSTRACT:
An apparatus for reading data from a memory in a computer system includes: an address register for holding an address to be supplied to the memory, a read data register for holding data read out from the memory and a device for generating a gated clock signal from a free-running clock signal having a predetermined constant period of time. The gated clock signal is free-running with the predetermined constant period of time in a normal clock mode but is generated by a single pulse with an interval longer than the period of the free-running clock signal in a single clock mode. A device, having serially connected plural registers for shifting a trigger signal in accordance with the free-running clock signal generates a read data clock signal. The trigger signal has a same timing synchronized with a specific phase of the gated clock signal at which a phase of the address register is switched to hold a new address to be supplied to the memory. The shifted trigger signal is fed to the read data register for hodling the data read out from the memory.

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