Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-11-06
2003-07-22
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185110, C365S185230
Reexamination Certificate
active
06597603
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to non-volatile memory integrated circuit devices, and more specifically to increasing the speed of programming such devices.
BACKGROUND ART
Non-volatile memory devices are used in the semiconductor integrated circuit industry in logic systems, such as microprocessors, and are used for creating storage elements such as memory boards or solid state hard disks. A conventional non-volatile or flash memory device includes a plurality of memory cells typically organized in the plurality of memory sectors. Within each memory sector, the memory cells are arranged in a array comprising a plurality of rows and a plurality of columns. A plurality of word lines are coupled to the respective rows of the memory cells, and a plurality of bit lines are coupled to the respective columns of the memory cells. Each memory cell is capable of storing one bit. During the operation of a conventional non-volatile memory, a memory cell is programmed by supplying a current from a high voltage power supply to the drain of the memory cell through the respective bit lines to which the memory cells are connected when the non-volatile memory is in a conventional embedded program mode.
With the advent of low and very low voltage flash non-volatile memories, operated at or below 2.7 V, the die area occupied by the on-chip voltage multiplier charge pump becomes prohibitively large. The reason for this increase in the size of the charge pump is explained below.
The open circuit voltage V
MO
of a n-stage charge pump is approximately given by formula (1)
V
MO
=n
(
V
DD
−V
TH
) (1)
where
n=numbers of stages
V
DD
=power supply voltage
V
TH
=average threshold voltage for NMOS transistors in the charge pump chain.
With reference to
FIG. 4
, a state-of-the-art charge pump
20
is shown. The internal charge pump
20
receives a low voltage power supply V
DD
at an input terminal
22
and produces a programming voltage V
M
at an output terminal
24
. A plurality of diode-connected NMOS transistors
215
are connected in series between the input terminal
22
and the output terminal
24
. Between each of the diode transistors
215
is a node
230
. A clock signal CLK is supplied to a clock input
28
and is inverted by an inverter
223
to provide an inverted clock signal {overscore (CLK)}
221
. The inverted clock signal
221
is inverted again by a second inverter
225
to provide a clock signal
212
. Capacitors
219
are connected between each of the nodes
230
and one of the clock signals
212
,
221
. Alternating nodes (N
1
, N
3
, N
5
) are connected to the clock signal line
212
through one of the capacitors
219
, while the other nodes (N
2
, N
4
, N
6
) are connected through a capacitor
219
to the inverted clock signal line
221
.
In
FIG. 4
, the internal nodes
230
are labeled N
k
, k=1, 2 . . . 6. The average voltage at node N
k
is
{tilde over (V)}
k
=k
(
V
DD
−{tilde over (V)}
THk
) (2)
The average threshold voltage {tilde over (V)}
THk
of the NMOS transistor at node N
k
is affected by the substrate bias provided by the average node voltage {tilde over (V)}
k
. Formula (3) provides an approximation of the substrate bias effect on increasing {tilde over (V)}
THk
:
{tilde over (V)}
THk
=V
THo
+&ggr;(
{square root over ({tilde over (V)})}
k
+&phgr;
B
−{square root over (&phgr;
B
)}) (3)
Where {tilde over (V)}
THo
is the threshold voltage at zero substrate bias, &ggr; is the substrate bias coefficient and &phgr;
B
is the built in substrate (bulk) voltage. Typical values are:
V
THo
≡0 for NMOS native transistors (No enhancement implant)
&ggr;≡0.1÷0.9{square root over (V)}
&phgr;
B
≡0.6÷0.7V
A trial and error iterative computation for V
MO
and {tilde over (V)}
TH
in formula (1) yields a typical value of {tilde over (V)}
TH
=1.5V for n=8÷10 stages. With reference to
FIG. 5
, the open circuit voltage V
MO
515
of the charge pump is plotted with respect to the power supply voltage V
DD
519
. Under load, V
M
has the approximate behavior:
V
~
M
=
V
~
MO
-
n
T
C
·
I
~
LOAD
(
4
)
where T=clock period, C=capacitor value. Assuming that {tilde over (V)}
Mnominal
should be {tilde over (V)}
Mnominal
=10V as imposed by the hot electron injection mechanism, the current capability of the charge pump is:
I
LOAD
max
=
V
~
Mo
-
V
~
M
nominal
n
T
C
(
5
)
provided that {tilde over (V)}
Mo
>{tilde over (V)}
Mnominl
. From
FIG. 5
, it can be seen from the graph
525
that the current capability
515
decreases dramatically for lower values of V
DD
519
.
Moreover, if one assumes that the programming cell current (Flash hot electron injection mechanism) is I
PRG CELL
≡200 &mgr;A., then the number of bits (q), i.e. memory cells, which can be simultaneously programmed is:
q
=
I
LOAD
max
I
PRG
CELL
=
V
~
Mo
-
V
~
M
nominal
n
·
T
C
·
I
PRG
CELL
(
6
)
q
=
n
(
V
DD
-
V
~
TH
)
-
V
M
nominal
n
·
T
C
·
I
PRG
CELL
(
7
)
q
=
·
C
T
·
n
(
V
DD
-
V
~
TH
)
-
V
M
nominal
I
PRG
CELL
(
8
)
Assuming that C=100 pF and T=100 ns, and using Equation (8) with the other numerical values assumed above, the following results are obtained:
n=10
{tilde over (V)}
TH
=1.5V
V
Mnominal
=10V
I
PREG CELL
=200 &mgr;A
C=100 pF
T=100 ns
q
=[5(
V
DD
−2.5)]bits(with
V
DD
in volts) (9)
Table 1 shows, in a second column, the number of bits that can be programmed at one time when the capacitance is 100 pF, based on various values of the power supply voltage V
DD
, shown in the first column. The third column of Table 1 shows the corresponding capacitance value when the programming rate is fixed at eight bits at a time for each of the power supply voltage V
DD
values of the first column.
TABLE 1
if C = 100
C for 8 bits at a
VDD (V)
pF q (bits)
time (pF)
5
[12.5]
12
64
4.5
[10]
10
80
4
[7.5]
7
107
3.5
[5]
5
160
3.0
[2.5]
2
320
2.5
[0]
0
∞
([] is integer part)
The following results can be observed from Table 1. At V
DD
=3V, one can either have C=100 pF and write only 2 bits at a time or, one can have C=320 pF and write 8 bits at a time. For comparison, at V
DD
=4.5V, one can either have C=100 pF and write 10 bits at a time or have C=80 pF and write 8 bits at a time. Therefore, to be able to write 8 bits at a time, and to reduce the internal voltage from V
DD
=4.5V down to V
DD
=3V, the area of the charge pump capacitors has to be increased by 400%
(
320
pF
80
pF
)
,
which is prohibitively large.
Attempts have been made in the prior art to increase the speed of programming flash non-volatile memories. U.S. Pat. No. 5,663,918 to Javanifard et al. discloses an integrated circuit having internal power supplies including circuitry for selecting either the external supply voltages or the internal power supplies to supply voltages to the remaining circuitry of the integrated circuit. The integrated circuit comprises voltage detector circuits for detecting the external voltage levels and a control circuit for selecting either the external supply voltages or the internal power supplies in response to the detected external voltages. The patent describes the mutually exclusive use of the external power supply and the operating supply voltage driven from the internal charge pump. Additionally, the regulation method is based upon the control of the frequency of the charge pump by means of a voltage control oscillator.
U.S. Pat. No. 6,014,332 to Roohparvar discloses a flash memory which includes circuitry to determine how many memory cells can be programm
Lambrache Emil
Smarandoiu George
Atmel Corporation
Ho Hoai
Schneck Thomas
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