Active solid-state devices (e.g. – transistors – solid-state diode – Bulk effect device – Intervalley transfer
Reexamination Certificate
2001-12-21
2003-02-11
Lebentritt, Michael S. (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Bulk effect device
Intervalley transfer
C257S011000, C257S026000, C257S495000, C257S625000, C257S905000
Reexamination Certificate
active
06518589
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to semiconductor devices and more particularly to a novel field effect transistor (FET) device and accompanying logic circuit that is multifunctional and selectively operates in two different modes, including in a mode that exhibits negative differential resistance (NDR). The present invention is applicable to a wide range of semiconductor integrated circuits, particularly for logic applications where it is desirable to achieve a high level of functional integration using multi-functional devices that can perform multiple boolean operations and/or multiple circuit operations.
BACKGROUND OF THE INVENTION
A new type of CMOS compatible, NDR capable FET is described in the aforementioned applications to King et al. referenced above. The advantages of such device are well set out in such materials, and are not repeated here. Nonetheless, in some environments, or during certain processing operations, it may be desirable to selectively disable the NDR capability of such device, and instead operate such device in a manner similar to that for any other conventional FET. This selective switching between modes is not practically possible with prior art NDR implementations (such as tunnel diodes for example) but if such were available it would make it feasible nonetheless to construct a multi-mode, multi-functional device. In other words, a single device could be constructed to perform more than one logical operation on one or more signal inputs. An improved device shown in U.S. Pat. No. 6,097,036 (incorporated by reference herein) details how a single semiconductor logic element can be constructed to perform more than one logic operation using a tunneling effect, but the latter mechanism is typically implemented with a GaAs (non-CMOS compatible) manufacturing process that is unattractive for mainstream semiconductor fabrication facilities. A similar limitation is apparent for the traditional resonant tunneling diode (RTD) based devices as depicted for example in
FIG. 3
of a reference from the Microelectronics Advanced Research Initiative entitled “Resonant Tunnelling Device Logic Circuits” Technical Report July 1998—July 1999 by Pascha et al., the entirety of which is incorporated herein. This reference illustrates a typical example of a monostable—bistable RTD inverter whose output varies depending on the state of an input clock. In other words, it can selectively induce an NDR effect in a tunneling diode so that in a non-NDR operating region the circuit has one type of output (linear or monostable) while in an NDR operating region the circuit has a bistable output. While this circuit is useful for large scale integrated logic circuits, it would be more useful to have an NDR device in which the actual NDR effect itself can be selectively enabled or disabled, so that in a non-NDR mode a device will not enter into an NDR operating region even with operating parameters which would otherwise be expected to induce such NDR effect.
SUMMARY Of THE INVENTION
Accordingly, an object of one aspect of the present invention is to provide an improved multi-mode FET that can be selectively controlled to operate in either an NDR mode or an non-NDR mode;
A related object of another aspect of the invention is to provide an improved multi-mode logic circuit employing the aforementioned multi-mode FET, and which can be programmed to perform two distinct logic operations, including a first type of logic operation in an NDR mode, and a second type of logic operation in a non-NDR mode;
A further object of the invention is to provide an improved multi-mode logic circuit that can be programmed and/or adjusted to perform two different boolean logic operations on a set of inputs, and/or two different circuit operations for a variable input;
A related object of the present invention is to provide a multi-terminal structure for controlling and programming the aforementioned multi-mode FET and/or multi-mode logic circuit, including the type of logic operation to be performed;
Yet another object of the present invention is to provide a new programmable logic FET which can be fabricated with a process that is fully compatible with conventional CMOS process technology, and yet be able to simultaneously provide more than one logical operation or function;
Another object of the present invention is to provide an improved multi-mode FET that is not based on heterostructure materials, or expensive fabrication techniques such as molecular beam epitaxy (MBE);
Another object of the present invention is to provide a new type of electronic logic circuit or logic family that can supplement and/or replace conventional semiconductor FET logic families, and in so doing effectuate new embodiments of common but critical logic circuits that are smaller, faster and more easily integrated;
Another object of the present invention is to introduce a new type of electronic logic family that has a number of useful characteristics and capabilities, including controlled programmable and re-programmable functionality at the single device level, and multiple simultaneous functionality, so that a new CMOS compatible logic building block can be provided for higher scale integrated circuits used in digital signal processors (DSPs) microprocessors, etc with a reduced gate count per logic function;
A further object of the invention is to provide a cost effective and reliable manufacturing method for making the aforementioned multi-mode FET and logic circuit, preferably using CMOS compatible processes that are easily integrable into commercial fabrication facilities.
These and other objects are achieved by the present invention that discloses an electronic device having a semiconductor structure adapted to selectively operate in a negative differential resistance mode through the use of a terminal coupled to a region of the semiconductor structure for receiving a mode selection signal. This mode selection signal selects whether the negative differential resistance mode is enabled or disabled; i.e., whether the device can exhibit NDR characteristics, or is limited to conventional FET characteristics. In a preferred embodiment, the semiconductor structure is substantially that of a four terminal FET that operates selectively in an NDR mode or a non-NDR mode through control of a bias signal applied to one of such terminals (e.g., a body terminal contact). The negative differential resistance mode is caused within a single semiconducting channel of the semiconductor structure at least in part by temporary electron trapping within a gate dielectric of the semiconductor structure. Stated another way, a negative differential resistance mode is created at least in part by dynamically varying the threshold voltage of the FET. The threshold voltage is adjusted by selectively removing hot carriers within the channel so as to set up a depletion region for reducing current carrier density in the channel. A trapping layer, adjacent to the channel, is used for temporarily trapping a sufficient number of carriers to cause the negative differential resistance mode.
The semiconductor structure is manufactured using standard complementary metal oxide semiconductor (CMOS) fabrication processes, including conventional masking, patterning, etching, thermal oxidation, implant, annealing, thermal treatment and deposition techniques normally used for making semiconductor devices. A multi-mode field effect transistor (FET) device is thus constructed through such processes to include: a first region configured as a source for the FET; a second region configured as a drain for the FET; and a third region configured to serve as a gate for the FET. The source and drain are coupled by a channel region which can be selectively controlled, under a suitable bias condition applied to the gate, to have a first negative differential resistance mode, or a second non-negative differential resistance mode. A fourth region acts as a body for the FET, and is configured to receive the aforementioned mode select signal. Thus, the structure is pre
Gross J. Nicholas
Lebentritt Michael S.
Progressant Technologies, Inc.
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