Dual-mode decoder circuit, integrated circuit memory array...

Details Dual-mode decoder circuit, integrated circuit memory array... Dual-mode decoder circuit, integrated circuit memory array...

2007-11-20

2007-11-20

Dinh, Son (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S063000, C365S201000

Reexamination Certificate

active

11026493

ABSTRACT:
In an embodiment of the invention an integrated circuit includes a memory array having a first plurality of decoded lines traversing across the memory array and a pair of dual-mode decoders, each decoder coupled to each of the plurality of decoded lines a respective location along said decoded lines, such as at opposite ends thereof. Both decoder circuits receive like address information. Normally both decoder circuits operate in a forward decode mode to decode the address information and drive a selected one of the decoded lines. During a test mode, one decoder is enabled in a reverse decode mode while the other decoder remains in a forward decode mode to verify proper decode operation and integrity of the decoded lines between the decoders.

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