Dual-mode clock for improved power management in a wireless...

Details Dual-mode clock for improved power management in a wireless... Dual-mode clock for improved power management in a wireless...

2008-01-22

2008-01-22

Jackson, Blane J. (Department: 2618)

Telecommunications

Receiver or analog modulated signal frequency converter

With particular receiver circuit

C455S256000, C455S574000, C370S311000

Reexamination Certificate

active

07321755

ABSTRACT:
A dual mode clock for providing first and second clock signals to a wireless interface unit. The first and second clock signals correspond to first and second operating states of the wireless interface unit. In the first operating state, the transceiver in the RF analog module is operational and the clock generator provides a first clock signal having low phase-noise characteristics necessary to maintain efficient operation of the transceiver. In a second operating state, the transceiver in the RF analog module is turned off. In this second operational state, the clock generator provides a second clock signal having a quality sufficient to maintain efficient operation of the digital baseband module in the wireless interface. By switching between low-power mode and normal mode, the system is operable to provide a high quality clock signal for use by the RF analog module when it is operational and to provide a lower power, lower quality clock signal which is sufficient for use by the baseband digital unit when the transceiver in the RF analog module is powered down.

REFERENCES:
patent: 2003/0060176 (2003-03-01), Heinonen et al.
patent: 2003/0144020 (2003-07-01), Challa et al.
patent: 2003/0173829 (2003-09-01), Zeng
patent: 2003/0203722 (2003-10-01), Karlquist et al.
patent: 2004/0097265 (2004-05-01), Cadieux et al.
patent: 2005/0043068 (2005-02-01), Shohara et al.

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