Dual memory timing system for VLSI test systems

Details Dual memory timing system for VLSI test systems Dual memory timing system for VLSI test systems

1989-11-13

1991-07-02

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307269, 328 63, 377 26, H03L 700, G01R 3128

Patent

active

050288784

ABSTRACT:
A timing system using shared address generator(s) to address memories that form the basis of each pin's timing reference generator can reduce the amount of hardware required to implement a "Timing Generator Per Pin" architecture in a VLSI tester by at least 50%.

REFERENCES:
patent: 4420696 (1983-12-01), Gemma et al.
patent: 4553100 (1985-11-01), Nishiura
patent: 4644195 (1987-02-01), Miller et al.
patent: 4855681 (1989-08-01), Millham

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