Dual-memory managing apparatus and method including prioritizati

Details Dual-memory managing apparatus and method including prioritizati Dual-memory managing apparatus and method including prioritizati

1996-09-10

1997-12-23

Swann, Tod R.

395473, 395492, 395841, 395468, G06F 1116, G06F 1216

Patent

active

057014370

ABSTRACT:
According to this invention, a dual-memory managing apparatus is applied to a system in which a plurality of memories and a plurality of processors are connected to each other through a data bus, and the dual-memory managing apparatus is a dual-memory managing apparatus for performing control performed when a memory copy operation from at least one first memory to at least one second memory system. The dual-memory managing apparatus includes a means for performing the memory copy operation for each word, and when write access from the plurality of processors to the plurality of memories is performed at almost the same timing as that of the memory copy operation, a control means for parallelly performing the memory write access and the memory copy operation when an address of the write access is different from an address subjected to the memory copy operation, and for preferentially performing the write access when the address of the write access is identical to the address subjected to the memory copy operation.

REFERENCES:
patent: 5193154 (1993-03-01), Kitajima et al.
patent: 5239637 (1993-08-01), Davis et al.
patent: 5247618 (1993-09-01), Davis et al.
patent: 5319766 (1994-06-01), Thauer et al.

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