Dual memory control circuit

Details Dual memory control circuit Dual memory control circuit

2000-03-27

2001-11-06

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S194000, C365S239000

Reexamination Certificate

active

06314046

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a memory control circuit, and more particularly, to a memory control circuit for controlling the writing and reading of data to or from a memory circuit.
When digital data undergoes an error correction process or an encoding/decoding process, various computation processes are performed on the digital data in block units. At this time, one block of digital data is stored in a buffer memory for a predetermined period to perform the computation process.
FIG. 1
is a schematic block diagram of a memory control circuit
100
.
A memory circuit
10
has a capacity enabling storage of at least one block of data that undergoes the computation process. The memory circuit
10
stores write data DIN provided from the memory control circuit
100
and reads the stored data. Read data DOUT is sequentially output from the memory circuit
10
. The memory circuit
10
is a synchronous memory which writes and reads data in accordance with a timing clock CK.
The memory control circuit
100
includes a control signal generation circuit
1
, an address generation circuit
2
, and a write data supply circuit
3
. In response to a data write command or a data read command provided by a microprocessor, the control signal generation circuit
1
generates a write enable signal WE, which permits a write operation to be performed in the memory circuit
10
, and a read enable signal RE, which permits a read operation to be performed. The control signal generation circuit
1
also generates a timing clock CK, which determines the operational timing of the memory circuit
10
. In response to an address command provided from the microprocessor together with the data write/read command, the address generation circuit
2
generates an address AD for the memory circuit
10
and provides the address AD to the memory circuit
10
. The write data supply circuit
3
receives data and holds the data. The held data is provided to the memory circuit
10
as the write data DIN.
The control signal generation circuit
1
generates the write enable signal WE, the read enable signal RE, and the timing clock CK in accordance with a reference clock BCK. During the write operation, the write data supply circuit
3
provides the write data DIN to the memory circuit
10
in accordance with the reference clock BCK. The address generation circuit
2
provides the write address AD of the data DIN, at the same time as the write enable signal WE, to the memory circuit
10
in accordance with the reference clock BCK. During the read operation, the address generation circuit
2
provides the read address AD, at the same time as the read enable signal RE, to the memory circuit
10
.
FIG. 2
is a timing chart illustrating the write operation performed for two consecutive data.
Write data D(n) is first held by the write data supply circuit
3
in response to the rising of the reference clock BCK. The write data D(n) is provided to the memory circuit
10
during one cycle of the reference clock BCK. Synchronously with the holding of the data D(n), the write enable signal WE rises in accordance with the write command, and a p address of the memory circuit
10
is designated by the address AD. The data D(n) is written to the p address of the memory circuit
10
in response to the rising of the timing clock CK. Data D(n+1) provided subsequent to the data D(n) is also written to the memory circuit
10
in the same manner as described above. At this time, the address AD is changed from the p address to a q address at a timing in which the write data D(n) is switched to the data D(n+1).
FIG. 3
is a timing chart illustrating the read operation of the data stored in the memory circuit
10
.
In accordance with the read command, the control signal generation circuit
1
causes the read enable signal RE to rise in response to the rising of the reference clock BCK and provides an address AD designating the p address to the memory circuit
10
. When the timing clock CK rises in this state, the data D(n) stored at the p address of the memory circuit
10
is read and read data DOUT is output from the memory circuit
10
. In response to the next rising edge of the reference clock BCK, the timing clock CK falls, and then the address AD is changed from the p address to the q address. In this state, when the timing clock CK rises again, the data D(n+1) stored at the q address of the memory circuit
10
is read and the read data DOUT is output from the memory circuit
10
.
The memory circuit
10
has the writing or reading of data repeated in cycles in accordance with the reference clock BCK. A shorter operation cycle of the memory circuit
10
is effective for increasing the speed for processing digital data. However, the operation cycle is limited within a range in which access to the memory circuit
10
is allowed.
The time required for the computation process of the digital data is determined by the access speed of the memory circuit
10
, which temporarily stores the digital data during the computation process. The access speed of the memory circuit
10
is determined by delays resulting from the circuit configuration in the memory circuit
10
. Thus, when the storage capacity of the memory circuit
10
is expanded and the circuit area is increased, an increase in the access speed becomes difficult. Accordingly, as the digital data increases, it becomes difficult to decrease the processing time.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a memory control circuit that writes and reads digital data at a high speed without increasing the memory circuit access speed.
A first aspect of the present invention provides a memory control circuit for controlling writing and reading consecutive data to and from first and second memory circuits. The memory control circuit includes a control signal generation circuit for generating a first write enable signal and a first read enable signal of the first memory circuit, an address generation circuit for generating an address signal designating a data write address of the first and second memory circuits, and a write data supply circuit for supplying write data to the first and second memory circuits. A shift circuit is connected between the control signal generation circuit and the second memory circuit to generate a second write enable signal and a second read enable signal by shifting the first write enable signal and the first read enable signal by one cycle of a data write cycle or read cycle. The write data is written alternately to the first and second memory circuits in accordance with an address signal and in response to the first and second write enable signals. The data written to the first and second memory circuits is read alternately from the first and second memory circuits in response to the first and second read enable signals.
A second aspect of the present invention provides a method for controlling writing and reading consecutive data to and from first and second memory circuits. A first write enable signal and a first read enable signal of the first memory circuit is first generated. An address signal which designates a data write address of the first and second memory circuits is then generated. Then, a second write enable signal and a second read enable signal are generated by shifting the first write enable signal and the first read enable signal by one cycle of a data write cycle or read cycle. The first and second memory circuits alternately write data in accordance with an address signal and in response to the first and second write enable signals. The first and second memory circuits alternately have the data written to the first and second memory circuits read in response to the first and second read enable signals.
Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.


REFERENCES:
patent: 4709264 (1987-11-01), Tam

Affiliated with

Also associated with

Rating

Dual memory control circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dual memory control circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual memory control circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2591292