Dual mask capacitor for integrated circuits

Semiconductor device manufacturing: process – Making passive device – Stacked capacitor

Reexamination Certificate

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Details

C438S239000, C438S250000, C438S253000, C257S068000, C257S071000

Reexamination Certificate

active

06924208

ABSTRACT:
An embodiment of the invention is a capacitor comprising a bottom electrode70coupled to a first interconnect30aof the top metal level10,a capacitor dielectric90,sidewalls105,and a top electrode110coupled to a second interconnect30bof the top metal level10.Another embodiment of the invention is a method of manufacturing a capacitor using a first mask140to form a material stack that includes a bottom electrode70coupled to a first interconnect30aof the top metal level10,a capacitor dielectric90,and a partial top electrode100.The method further includes using a second mask150to form a complete top electrode coupled to a second interconnect30bof the top metal level10.

REFERENCES:
patent: 5563762 (1996-10-01), Leung et al.

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